1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix_pci.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/pci-host/q35.h" 32 33 /**************************************************************************** 34 * Q35 host 35 */ 36 37 static int q35_host_init(SysBusDevice *dev) 38 { 39 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 40 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 41 42 memory_region_init_io(&pci->conf_mem, OBJECT(pci), &pci_host_conf_le_ops, pci, 43 "pci-conf-idx", 4); 44 sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 45 sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 46 47 memory_region_init_io(&pci->data_mem, OBJECT(pci), &pci_host_data_le_ops, pci, 48 "pci-conf-data", 4); 49 sysbus_add_io(dev, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 50 sysbus_init_ioports(dev, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 51 52 if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { 53 return -1; 54 } 55 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 56 s->mch.pci_address_space, s->mch.address_space_io, 57 0, TYPE_PCIE_BUS); 58 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 59 qdev_init_nofail(DEVICE(&s->mch)); 60 61 return 0; 62 } 63 64 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 65 PCIBus *rootbus) 66 { 67 /* For backwards compat with old device paths */ 68 return "0000"; 69 } 70 71 static Property mch_props[] = { 72 DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr, 73 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 74 DEFINE_PROP_END_OF_LIST(), 75 }; 76 77 static void q35_host_class_init(ObjectClass *klass, void *data) 78 { 79 DeviceClass *dc = DEVICE_CLASS(klass); 80 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 81 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 82 83 hc->root_bus_path = q35_host_root_bus_path; 84 k->init = q35_host_init; 85 dc->props = mch_props; 86 dc->fw_name = "pci"; 87 } 88 89 static void q35_host_initfn(Object *obj) 90 { 91 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 92 93 object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); 94 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 95 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 96 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 97 } 98 99 static const TypeInfo q35_host_info = { 100 .name = TYPE_Q35_HOST_DEVICE, 101 .parent = TYPE_PCIE_HOST_BRIDGE, 102 .instance_size = sizeof(Q35PCIHost), 103 .instance_init = q35_host_initfn, 104 .class_init = q35_host_class_init, 105 }; 106 107 /**************************************************************************** 108 * MCH D0:F0 109 */ 110 111 /* PCIe MMCFG */ 112 static void mch_update_pciexbar(MCHPCIState *mch) 113 { 114 PCIDevice *pci_dev = PCI_DEVICE(mch); 115 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 116 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 117 118 uint64_t pciexbar; 119 int enable; 120 uint64_t addr; 121 uint64_t addr_mask; 122 uint32_t length; 123 124 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 125 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 126 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 127 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 128 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 129 length = 256 * 1024 * 1024; 130 break; 131 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 132 length = 128 * 1024 * 1024; 133 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 134 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 135 break; 136 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 137 length = 64 * 1024 * 1024; 138 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 139 break; 140 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 141 default: 142 enable = 0; 143 length = 0; 144 abort(); 145 break; 146 } 147 addr = pciexbar & addr_mask; 148 pcie_host_mmcfg_update(pehb, enable, addr, length); 149 } 150 151 /* PAM */ 152 static void mch_update_pam(MCHPCIState *mch) 153 { 154 PCIDevice *pd = PCI_DEVICE(mch); 155 int i; 156 157 memory_region_transaction_begin(); 158 for (i = 0; i < 13; i++) { 159 pam_update(&mch->pam_regions[i], i, 160 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 161 } 162 memory_region_transaction_commit(); 163 } 164 165 /* SMRAM */ 166 static void mch_update_smram(MCHPCIState *mch) 167 { 168 PCIDevice *pd = PCI_DEVICE(mch); 169 170 memory_region_transaction_begin(); 171 smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], 172 mch->smm_enabled); 173 memory_region_transaction_commit(); 174 } 175 176 static void mch_set_smm(int smm, void *arg) 177 { 178 MCHPCIState *mch = arg; 179 PCIDevice *pd = PCI_DEVICE(mch); 180 181 memory_region_transaction_begin(); 182 smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], 183 &mch->smram_region); 184 memory_region_transaction_commit(); 185 } 186 187 static void mch_write_config(PCIDevice *d, 188 uint32_t address, uint32_t val, int len) 189 { 190 MCHPCIState *mch = MCH_PCI_DEVICE(d); 191 192 /* XXX: implement SMRAM.D_LOCK */ 193 pci_default_write_config(d, address, val, len); 194 195 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 196 MCH_HOST_BRIDGE_PAM_SIZE)) { 197 mch_update_pam(mch); 198 } 199 200 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 201 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 202 mch_update_pciexbar(mch); 203 } 204 205 if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 206 MCH_HOST_BRDIGE_SMRAM_SIZE)) { 207 mch_update_smram(mch); 208 } 209 } 210 211 static void mch_update(MCHPCIState *mch) 212 { 213 mch_update_pciexbar(mch); 214 mch_update_pam(mch); 215 mch_update_smram(mch); 216 } 217 218 static int mch_post_load(void *opaque, int version_id) 219 { 220 MCHPCIState *mch = opaque; 221 mch_update(mch); 222 return 0; 223 } 224 225 static const VMStateDescription vmstate_mch = { 226 .name = "mch", 227 .version_id = 1, 228 .minimum_version_id = 1, 229 .minimum_version_id_old = 1, 230 .post_load = mch_post_load, 231 .fields = (VMStateField []) { 232 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 233 VMSTATE_UINT8(smm_enabled, MCHPCIState), 234 VMSTATE_END_OF_LIST() 235 } 236 }; 237 238 static void mch_reset(DeviceState *qdev) 239 { 240 PCIDevice *d = PCI_DEVICE(qdev); 241 MCHPCIState *mch = MCH_PCI_DEVICE(d); 242 243 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 244 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 245 246 d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 247 248 mch_update(mch); 249 } 250 251 static int mch_init(PCIDevice *d) 252 { 253 int i; 254 hwaddr pci_hole64_size; 255 MCHPCIState *mch = MCH_PCI_DEVICE(d); 256 257 /* Leave enough space for the biggest MCFG BAR */ 258 /* TODO: this matches current bios behaviour, but 259 * it's not a power of two, which means an MTRR 260 * can't cover it exactly. 261 */ 262 mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 263 MCH_HOST_BRIDGE_PCIEXBAR_MAX; 264 265 /* setup pci memory regions */ 266 memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", 267 mch->pci_address_space, 268 mch->below_4g_mem_size, 269 0x100000000ULL - mch->below_4g_mem_size); 270 memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 271 &mch->pci_hole); 272 pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : 273 ((uint64_t)1 << 62)); 274 memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", 275 mch->pci_address_space, 276 0x100000000ULL + mch->above_4g_mem_size, 277 pci_hole64_size); 278 if (pci_hole64_size) { 279 memory_region_add_subregion(mch->system_memory, 280 0x100000000ULL + mch->above_4g_mem_size, 281 &mch->pci_hole_64bit); 282 } 283 /* smram */ 284 cpu_smm_register(&mch_set_smm, mch); 285 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 286 mch->pci_address_space, 0xa0000, 0x20000); 287 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 288 &mch->smram_region, 1); 289 memory_region_set_enabled(&mch->smram_region, false); 290 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 291 &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 292 for (i = 0; i < 12; ++i) { 293 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 294 &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 295 PAM_EXPAN_SIZE); 296 } 297 return 0; 298 } 299 300 static void mch_class_init(ObjectClass *klass, void *data) 301 { 302 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 303 DeviceClass *dc = DEVICE_CLASS(klass); 304 305 k->init = mch_init; 306 k->config_write = mch_write_config; 307 dc->reset = mch_reset; 308 dc->desc = "Host bridge"; 309 dc->vmsd = &vmstate_mch; 310 k->vendor_id = PCI_VENDOR_ID_INTEL; 311 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 312 k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; 313 k->class_id = PCI_CLASS_BRIDGE_HOST; 314 } 315 316 static const TypeInfo mch_info = { 317 .name = TYPE_MCH_PCI_DEVICE, 318 .parent = TYPE_PCI_DEVICE, 319 .instance_size = sizeof(MCHPCIState), 320 .class_init = mch_class_init, 321 }; 322 323 static void q35_register(void) 324 { 325 type_register_static(&mch_info); 326 type_register_static(&q35_host_info); 327 } 328 329 type_init(q35_register); 330