1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix_pci.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/pci-host/q35.h" 32 #include "qapi/visitor.h" 33 34 /**************************************************************************** 35 * Q35 host 36 */ 37 38 static void q35_host_realize(DeviceState *dev, Error **errp) 39 { 40 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 41 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 42 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 43 44 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 45 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 46 47 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 48 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 49 50 if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { 51 error_setg(errp, "failed to initialize pcie host"); 52 return; 53 } 54 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 55 s->mch.pci_address_space, s->mch.address_space_io, 56 0, TYPE_PCIE_BUS); 57 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 58 qdev_init_nofail(DEVICE(&s->mch)); 59 } 60 61 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 62 PCIBus *rootbus) 63 { 64 /* For backwards compat with old device paths */ 65 return "0000"; 66 } 67 68 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 69 void *opaque, const char *name, 70 Error **errp) 71 { 72 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 73 uint32_t value = s->mch.pci_info.w32.begin; 74 75 visit_type_uint32(v, &value, name, errp); 76 } 77 78 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 79 void *opaque, const char *name, 80 Error **errp) 81 { 82 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 83 uint32_t value = s->mch.pci_info.w32.end; 84 85 visit_type_uint32(v, &value, name, errp); 86 } 87 88 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 89 void *opaque, const char *name, 90 Error **errp) 91 { 92 PCIHostState *h = PCI_HOST_BRIDGE(obj); 93 Range w64; 94 95 pci_bus_get_w64_range(h->bus, &w64); 96 97 visit_type_uint64(v, &w64.begin, name, errp); 98 } 99 100 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 101 void *opaque, const char *name, 102 Error **errp) 103 { 104 PCIHostState *h = PCI_HOST_BRIDGE(obj); 105 Range w64; 106 107 pci_bus_get_w64_range(h->bus, &w64); 108 109 visit_type_uint64(v, &w64.end, name, errp); 110 } 111 112 static Property mch_props[] = { 113 DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr, 114 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 115 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 116 mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 117 DEFINE_PROP_END_OF_LIST(), 118 }; 119 120 static void q35_host_class_init(ObjectClass *klass, void *data) 121 { 122 DeviceClass *dc = DEVICE_CLASS(klass); 123 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 124 125 hc->root_bus_path = q35_host_root_bus_path; 126 dc->realize = q35_host_realize; 127 dc->props = mch_props; 128 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 129 dc->fw_name = "pci"; 130 } 131 132 static void q35_host_initfn(Object *obj) 133 { 134 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 135 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 136 137 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 138 "pci-conf-idx", 4); 139 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 140 "pci-conf-data", 4); 141 142 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 143 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 144 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 145 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 146 147 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 148 q35_host_get_pci_hole_start, 149 NULL, NULL, NULL, NULL); 150 151 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 152 q35_host_get_pci_hole_end, 153 NULL, NULL, NULL, NULL); 154 155 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 156 q35_host_get_pci_hole64_start, 157 NULL, NULL, NULL, NULL); 158 159 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 160 q35_host_get_pci_hole64_end, 161 NULL, NULL, NULL, NULL); 162 163 /* Leave enough space for the biggest MCFG BAR */ 164 /* TODO: this matches current bios behaviour, but 165 * it's not a power of two, which means an MTRR 166 * can't cover it exactly. 167 */ 168 s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 169 MCH_HOST_BRIDGE_PCIEXBAR_MAX; 170 s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 171 } 172 173 static const TypeInfo q35_host_info = { 174 .name = TYPE_Q35_HOST_DEVICE, 175 .parent = TYPE_PCIE_HOST_BRIDGE, 176 .instance_size = sizeof(Q35PCIHost), 177 .instance_init = q35_host_initfn, 178 .class_init = q35_host_class_init, 179 }; 180 181 /**************************************************************************** 182 * MCH D0:F0 183 */ 184 185 /* PCIe MMCFG */ 186 static void mch_update_pciexbar(MCHPCIState *mch) 187 { 188 PCIDevice *pci_dev = PCI_DEVICE(mch); 189 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 190 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 191 192 uint64_t pciexbar; 193 int enable; 194 uint64_t addr; 195 uint64_t addr_mask; 196 uint32_t length; 197 198 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 199 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 200 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 201 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 202 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 203 length = 256 * 1024 * 1024; 204 break; 205 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 206 length = 128 * 1024 * 1024; 207 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 208 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 209 break; 210 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 211 length = 64 * 1024 * 1024; 212 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 213 break; 214 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 215 default: 216 enable = 0; 217 length = 0; 218 abort(); 219 break; 220 } 221 addr = pciexbar & addr_mask; 222 pcie_host_mmcfg_update(pehb, enable, addr, length); 223 /* Leave enough space for the MCFG BAR */ 224 /* 225 * TODO: this matches current bios behaviour, but it's not a power of two, 226 * which means an MTRR can't cover it exactly. 227 */ 228 if (enable) { 229 mch->pci_info.w32.begin = addr + length; 230 } else { 231 mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 232 } 233 } 234 235 /* PAM */ 236 static void mch_update_pam(MCHPCIState *mch) 237 { 238 PCIDevice *pd = PCI_DEVICE(mch); 239 int i; 240 241 memory_region_transaction_begin(); 242 for (i = 0; i < 13; i++) { 243 pam_update(&mch->pam_regions[i], i, 244 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 245 } 246 memory_region_transaction_commit(); 247 } 248 249 /* SMRAM */ 250 static void mch_update_smram(MCHPCIState *mch) 251 { 252 PCIDevice *pd = PCI_DEVICE(mch); 253 254 memory_region_transaction_begin(); 255 smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], 256 mch->smm_enabled); 257 memory_region_transaction_commit(); 258 } 259 260 static void mch_set_smm(int smm, void *arg) 261 { 262 MCHPCIState *mch = arg; 263 PCIDevice *pd = PCI_DEVICE(mch); 264 265 memory_region_transaction_begin(); 266 smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], 267 &mch->smram_region); 268 memory_region_transaction_commit(); 269 } 270 271 static void mch_write_config(PCIDevice *d, 272 uint32_t address, uint32_t val, int len) 273 { 274 MCHPCIState *mch = MCH_PCI_DEVICE(d); 275 276 /* XXX: implement SMRAM.D_LOCK */ 277 pci_default_write_config(d, address, val, len); 278 279 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 280 MCH_HOST_BRIDGE_PAM_SIZE)) { 281 mch_update_pam(mch); 282 } 283 284 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 285 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 286 mch_update_pciexbar(mch); 287 } 288 289 if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 290 MCH_HOST_BRDIGE_SMRAM_SIZE)) { 291 mch_update_smram(mch); 292 } 293 } 294 295 static void mch_update(MCHPCIState *mch) 296 { 297 mch_update_pciexbar(mch); 298 mch_update_pam(mch); 299 mch_update_smram(mch); 300 } 301 302 static int mch_post_load(void *opaque, int version_id) 303 { 304 MCHPCIState *mch = opaque; 305 mch_update(mch); 306 return 0; 307 } 308 309 static const VMStateDescription vmstate_mch = { 310 .name = "mch", 311 .version_id = 1, 312 .minimum_version_id = 1, 313 .minimum_version_id_old = 1, 314 .post_load = mch_post_load, 315 .fields = (VMStateField []) { 316 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 317 VMSTATE_UINT8(smm_enabled, MCHPCIState), 318 VMSTATE_END_OF_LIST() 319 } 320 }; 321 322 static void mch_reset(DeviceState *qdev) 323 { 324 PCIDevice *d = PCI_DEVICE(qdev); 325 MCHPCIState *mch = MCH_PCI_DEVICE(d); 326 327 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 328 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 329 330 d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 331 332 mch_update(mch); 333 } 334 335 static int mch_init(PCIDevice *d) 336 { 337 int i; 338 MCHPCIState *mch = MCH_PCI_DEVICE(d); 339 uint64_t pci_hole64_size; 340 341 /* setup pci memory regions */ 342 memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", 343 mch->pci_address_space, 344 mch->below_4g_mem_size, 345 0x100000000ULL - mch->below_4g_mem_size); 346 memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 347 &mch->pci_hole); 348 349 pci_hole64_size = pci_host_get_hole64_size(mch->pci_hole64_size); 350 pc_init_pci64_hole(&mch->pci_info, 0x100000000ULL + mch->above_4g_mem_size, 351 pci_hole64_size); 352 memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", 353 mch->pci_address_space, 354 mch->pci_info.w64.begin, 355 pci_hole64_size); 356 if (pci_hole64_size) { 357 memory_region_add_subregion(mch->system_memory, 358 mch->pci_info.w64.begin, 359 &mch->pci_hole_64bit); 360 } 361 /* smram */ 362 cpu_smm_register(&mch_set_smm, mch); 363 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 364 mch->pci_address_space, 0xa0000, 0x20000); 365 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 366 &mch->smram_region, 1); 367 memory_region_set_enabled(&mch->smram_region, false); 368 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 369 &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 370 for (i = 0; i < 12; ++i) { 371 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 372 &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 373 PAM_EXPAN_SIZE); 374 } 375 return 0; 376 } 377 378 static void mch_class_init(ObjectClass *klass, void *data) 379 { 380 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 381 DeviceClass *dc = DEVICE_CLASS(klass); 382 383 k->init = mch_init; 384 k->config_write = mch_write_config; 385 dc->reset = mch_reset; 386 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 387 dc->desc = "Host bridge"; 388 dc->vmsd = &vmstate_mch; 389 k->vendor_id = PCI_VENDOR_ID_INTEL; 390 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 391 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 392 k->class_id = PCI_CLASS_BRIDGE_HOST; 393 } 394 395 static const TypeInfo mch_info = { 396 .name = TYPE_MCH_PCI_DEVICE, 397 .parent = TYPE_PCI_DEVICE, 398 .instance_size = sizeof(MCHPCIState), 399 .class_init = mch_class_init, 400 }; 401 402 static void q35_register(void) 403 { 404 type_register_static(&mch_info); 405 type_register_static(&q35_host_info); 406 } 407 408 type_init(q35_register); 409