1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/pci-host/q35.h" 33 #include "qapi/error.h" 34 #include "qapi/visitor.h" 35 36 /**************************************************************************** 37 * Q35 host 38 */ 39 40 static void q35_host_realize(DeviceState *dev, Error **errp) 41 { 42 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 43 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 44 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 45 46 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 47 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 48 49 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 50 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 51 52 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 53 s->mch.pci_address_space, s->mch.address_space_io, 54 0, TYPE_PCIE_BUS); 55 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 56 qdev_init_nofail(DEVICE(&s->mch)); 57 } 58 59 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 60 PCIBus *rootbus) 61 { 62 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 63 64 /* For backwards compat with old device paths */ 65 if (s->mch.short_root_bus) { 66 return "0000"; 67 } 68 return "0000:00"; 69 } 70 71 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 72 const char *name, void *opaque, 73 Error **errp) 74 { 75 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 76 uint32_t value = s->mch.pci_info.w32.begin; 77 78 visit_type_uint32(v, name, &value, errp); 79 } 80 81 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 82 const char *name, void *opaque, 83 Error **errp) 84 { 85 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 86 uint32_t value = s->mch.pci_info.w32.end; 87 88 visit_type_uint32(v, name, &value, errp); 89 } 90 91 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 92 const char *name, void *opaque, 93 Error **errp) 94 { 95 PCIHostState *h = PCI_HOST_BRIDGE(obj); 96 Range w64; 97 98 pci_bus_get_w64_range(h->bus, &w64); 99 100 visit_type_uint64(v, name, &w64.begin, errp); 101 } 102 103 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 104 const char *name, void *opaque, 105 Error **errp) 106 { 107 PCIHostState *h = PCI_HOST_BRIDGE(obj); 108 Range w64; 109 110 pci_bus_get_w64_range(h->bus, &w64); 111 112 visit_type_uint64(v, name, &w64.end, errp); 113 } 114 115 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 116 void *opaque, Error **errp) 117 { 118 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 119 uint32_t value = e->size; 120 121 visit_type_uint32(v, name, &value, errp); 122 } 123 124 static Property mch_props[] = { 125 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 126 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 127 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 128 mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 129 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 130 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 131 mch.below_4g_mem_size, 0), 132 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 133 mch.above_4g_mem_size, 0), 134 DEFINE_PROP_END_OF_LIST(), 135 }; 136 137 static void q35_host_class_init(ObjectClass *klass, void *data) 138 { 139 DeviceClass *dc = DEVICE_CLASS(klass); 140 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 141 142 hc->root_bus_path = q35_host_root_bus_path; 143 dc->realize = q35_host_realize; 144 dc->props = mch_props; 145 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 146 dc->fw_name = "pci"; 147 } 148 149 static void q35_host_initfn(Object *obj) 150 { 151 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 152 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 153 154 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 155 "pci-conf-idx", 4); 156 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 157 "pci-conf-data", 4); 158 159 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 160 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 161 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 162 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 163 164 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 165 q35_host_get_pci_hole_start, 166 NULL, NULL, NULL, NULL); 167 168 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 169 q35_host_get_pci_hole_end, 170 NULL, NULL, NULL, NULL); 171 172 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 173 q35_host_get_pci_hole64_start, 174 NULL, NULL, NULL, NULL); 175 176 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 177 q35_host_get_pci_hole64_end, 178 NULL, NULL, NULL, NULL); 179 180 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", 181 q35_host_get_mmcfg_size, 182 NULL, NULL, NULL, NULL); 183 184 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 185 (Object **) &s->mch.ram_memory, 186 qdev_prop_allow_set_link_before_realize, 0, NULL); 187 188 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 189 (Object **) &s->mch.pci_address_space, 190 qdev_prop_allow_set_link_before_realize, 0, NULL); 191 192 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 193 (Object **) &s->mch.system_memory, 194 qdev_prop_allow_set_link_before_realize, 0, NULL); 195 196 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 197 (Object **) &s->mch.address_space_io, 198 qdev_prop_allow_set_link_before_realize, 0, NULL); 199 200 /* Leave enough space for the biggest MCFG BAR */ 201 /* TODO: this matches current bios behaviour, but 202 * it's not a power of two, which means an MTRR 203 * can't cover it exactly. 204 */ 205 s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 206 MCH_HOST_BRIDGE_PCIEXBAR_MAX; 207 s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 208 } 209 210 static const TypeInfo q35_host_info = { 211 .name = TYPE_Q35_HOST_DEVICE, 212 .parent = TYPE_PCIE_HOST_BRIDGE, 213 .instance_size = sizeof(Q35PCIHost), 214 .instance_init = q35_host_initfn, 215 .class_init = q35_host_class_init, 216 }; 217 218 /**************************************************************************** 219 * MCH D0:F0 220 */ 221 222 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 223 { 224 return 0xffffffff; 225 } 226 227 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 228 unsigned width) 229 { 230 /* nothing */ 231 } 232 233 static const MemoryRegionOps tseg_blackhole_ops = { 234 .read = tseg_blackhole_read, 235 .write = tseg_blackhole_write, 236 .endianness = DEVICE_NATIVE_ENDIAN, 237 .valid.min_access_size = 1, 238 .valid.max_access_size = 4, 239 .impl.min_access_size = 4, 240 .impl.max_access_size = 4, 241 .endianness = DEVICE_LITTLE_ENDIAN, 242 }; 243 244 /* PCIe MMCFG */ 245 static void mch_update_pciexbar(MCHPCIState *mch) 246 { 247 PCIDevice *pci_dev = PCI_DEVICE(mch); 248 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 249 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 250 251 uint64_t pciexbar; 252 int enable; 253 uint64_t addr; 254 uint64_t addr_mask; 255 uint32_t length; 256 257 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 258 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 259 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 260 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 261 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 262 length = 256 * 1024 * 1024; 263 break; 264 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 265 length = 128 * 1024 * 1024; 266 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 267 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 268 break; 269 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 270 length = 64 * 1024 * 1024; 271 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 272 break; 273 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 274 default: 275 enable = 0; 276 length = 0; 277 abort(); 278 break; 279 } 280 addr = pciexbar & addr_mask; 281 pcie_host_mmcfg_update(pehb, enable, addr, length); 282 /* Leave enough space for the MCFG BAR */ 283 /* 284 * TODO: this matches current bios behaviour, but it's not a power of two, 285 * which means an MTRR can't cover it exactly. 286 */ 287 if (enable) { 288 mch->pci_info.w32.begin = addr + length; 289 } else { 290 mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 291 } 292 } 293 294 /* PAM */ 295 static void mch_update_pam(MCHPCIState *mch) 296 { 297 PCIDevice *pd = PCI_DEVICE(mch); 298 int i; 299 300 memory_region_transaction_begin(); 301 for (i = 0; i < 13; i++) { 302 pam_update(&mch->pam_regions[i], i, 303 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 304 } 305 memory_region_transaction_commit(); 306 } 307 308 /* SMRAM */ 309 static void mch_update_smram(MCHPCIState *mch) 310 { 311 PCIDevice *pd = PCI_DEVICE(mch); 312 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 313 uint32_t tseg_size; 314 315 /* implement SMRAM.D_LCK */ 316 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 317 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 318 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 319 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 320 } 321 322 memory_region_transaction_begin(); 323 324 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 325 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 326 memory_region_set_enabled(&mch->smram_region, h_smrame); 327 /* Show high SMRAM if H_SMRAME = 1 */ 328 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 329 } else { 330 /* Hide high SMRAM and low SMRAM */ 331 memory_region_set_enabled(&mch->smram_region, true); 332 memory_region_set_enabled(&mch->open_high_smram, false); 333 } 334 335 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 336 memory_region_set_enabled(&mch->low_smram, !h_smrame); 337 memory_region_set_enabled(&mch->high_smram, h_smrame); 338 } else { 339 memory_region_set_enabled(&mch->low_smram, false); 340 memory_region_set_enabled(&mch->high_smram, false); 341 } 342 343 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 344 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 345 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 346 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 347 tseg_size = 1024 * 1024; 348 break; 349 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 350 tseg_size = 1024 * 1024 * 2; 351 break; 352 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 353 tseg_size = 1024 * 1024 * 8; 354 break; 355 default: 356 tseg_size = 0; 357 break; 358 } 359 } else { 360 tseg_size = 0; 361 } 362 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 363 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 364 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 365 memory_region_add_subregion_overlap(mch->system_memory, 366 mch->below_4g_mem_size - tseg_size, 367 &mch->tseg_blackhole, 1); 368 369 memory_region_set_enabled(&mch->tseg_window, tseg_size); 370 memory_region_set_size(&mch->tseg_window, tseg_size); 371 memory_region_set_address(&mch->tseg_window, 372 mch->below_4g_mem_size - tseg_size); 373 memory_region_set_alias_offset(&mch->tseg_window, 374 mch->below_4g_mem_size - tseg_size); 375 376 memory_region_transaction_commit(); 377 } 378 379 static void mch_write_config(PCIDevice *d, 380 uint32_t address, uint32_t val, int len) 381 { 382 MCHPCIState *mch = MCH_PCI_DEVICE(d); 383 384 pci_default_write_config(d, address, val, len); 385 386 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 387 MCH_HOST_BRIDGE_PAM_SIZE)) { 388 mch_update_pam(mch); 389 } 390 391 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 392 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 393 mch_update_pciexbar(mch); 394 } 395 396 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 397 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 398 mch_update_smram(mch); 399 } 400 } 401 402 static void mch_update(MCHPCIState *mch) 403 { 404 mch_update_pciexbar(mch); 405 mch_update_pam(mch); 406 mch_update_smram(mch); 407 } 408 409 static int mch_post_load(void *opaque, int version_id) 410 { 411 MCHPCIState *mch = opaque; 412 mch_update(mch); 413 return 0; 414 } 415 416 static const VMStateDescription vmstate_mch = { 417 .name = "mch", 418 .version_id = 1, 419 .minimum_version_id = 1, 420 .post_load = mch_post_load, 421 .fields = (VMStateField[]) { 422 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 423 /* Used to be smm_enabled, which was basically always zero because 424 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 425 */ 426 VMSTATE_UNUSED(1), 427 VMSTATE_END_OF_LIST() 428 } 429 }; 430 431 static void mch_reset(DeviceState *qdev) 432 { 433 PCIDevice *d = PCI_DEVICE(qdev); 434 MCHPCIState *mch = MCH_PCI_DEVICE(d); 435 436 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 437 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 438 439 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 440 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 441 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 442 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 443 444 mch_update(mch); 445 } 446 447 static AddressSpace *q35_host_dma_iommu(PCIBus *bus, void *opaque, int devfn) 448 { 449 IntelIOMMUState *s = opaque; 450 VTDAddressSpace *vtd_as; 451 452 assert(0 <= devfn && devfn <= VTD_PCI_DEVFN_MAX); 453 454 vtd_as = vtd_find_add_as(s, bus, devfn); 455 return &vtd_as->as; 456 } 457 458 static void mch_init_dmar(MCHPCIState *mch) 459 { 460 PCIBus *pci_bus = PCI_BUS(qdev_get_parent_bus(DEVICE(mch))); 461 462 mch->iommu = INTEL_IOMMU_DEVICE(qdev_create(NULL, TYPE_INTEL_IOMMU_DEVICE)); 463 object_property_add_child(OBJECT(mch), "intel-iommu", 464 OBJECT(mch->iommu), NULL); 465 qdev_init_nofail(DEVICE(mch->iommu)); 466 sysbus_mmio_map(SYS_BUS_DEVICE(mch->iommu), 0, Q35_HOST_BRIDGE_IOMMU_ADDR); 467 468 pci_setup_iommu(pci_bus, q35_host_dma_iommu, mch->iommu); 469 } 470 471 static void mch_realize(PCIDevice *d, Error **errp) 472 { 473 int i; 474 MCHPCIState *mch = MCH_PCI_DEVICE(d); 475 476 /* setup pci memory mapping */ 477 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 478 mch->pci_address_space); 479 480 /* if *disabled* show SMRAM to all CPUs */ 481 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 482 mch->pci_address_space, 0xa0000, 0x20000); 483 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 484 &mch->smram_region, 1); 485 memory_region_set_enabled(&mch->smram_region, true); 486 487 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 488 mch->ram_memory, 0xa0000, 0x20000); 489 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 490 &mch->open_high_smram, 1); 491 memory_region_set_enabled(&mch->open_high_smram, false); 492 493 /* smram, as seen by SMM CPUs */ 494 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 495 memory_region_set_enabled(&mch->smram, true); 496 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 497 mch->ram_memory, 0xa0000, 0x20000); 498 memory_region_set_enabled(&mch->low_smram, true); 499 memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 500 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 501 mch->ram_memory, 0xa0000, 0x20000); 502 memory_region_set_enabled(&mch->high_smram, true); 503 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 504 505 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 506 &tseg_blackhole_ops, NULL, 507 "tseg-blackhole", 0); 508 memory_region_set_enabled(&mch->tseg_blackhole, false); 509 memory_region_add_subregion_overlap(mch->system_memory, 510 mch->below_4g_mem_size, 511 &mch->tseg_blackhole, 1); 512 513 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 514 mch->ram_memory, mch->below_4g_mem_size, 0); 515 memory_region_set_enabled(&mch->tseg_window, false); 516 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 517 &mch->tseg_window); 518 object_property_add_const_link(qdev_get_machine(), "smram", 519 OBJECT(&mch->smram), &error_abort); 520 521 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 522 mch->pci_address_space, &mch->pam_regions[0], 523 PAM_BIOS_BASE, PAM_BIOS_SIZE); 524 for (i = 0; i < 12; ++i) { 525 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 526 mch->pci_address_space, &mch->pam_regions[i+1], 527 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 528 } 529 /* Intel IOMMU (VT-d) */ 530 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { 531 mch_init_dmar(mch); 532 } 533 } 534 535 uint64_t mch_mcfg_base(void) 536 { 537 bool ambiguous; 538 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 539 if (!o) { 540 return 0; 541 } 542 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 543 } 544 545 static void mch_class_init(ObjectClass *klass, void *data) 546 { 547 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 548 DeviceClass *dc = DEVICE_CLASS(klass); 549 550 k->realize = mch_realize; 551 k->config_write = mch_write_config; 552 dc->reset = mch_reset; 553 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 554 dc->desc = "Host bridge"; 555 dc->vmsd = &vmstate_mch; 556 k->vendor_id = PCI_VENDOR_ID_INTEL; 557 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 558 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 559 k->class_id = PCI_CLASS_BRIDGE_HOST; 560 /* 561 * PCI-facing part of the host bridge, not usable without the 562 * host-facing part, which can't be device_add'ed, yet. 563 */ 564 dc->cannot_instantiate_with_device_add_yet = true; 565 } 566 567 static const TypeInfo mch_info = { 568 .name = TYPE_MCH_PCI_DEVICE, 569 .parent = TYPE_PCI_DEVICE, 570 .instance_size = sizeof(MCHPCIState), 571 .class_init = mch_class_init, 572 }; 573 574 static void q35_register(void) 575 { 576 type_register_static(&mch_info); 577 type_register_static(&q35_host_info); 578 } 579 580 type_init(q35_register); 581