1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "qemu/log.h" 33 #include "hw/i386/pc.h" 34 #include "hw/pci-host/q35.h" 35 #include "hw/qdev-properties.h" 36 #include "migration/vmstate.h" 37 #include "qapi/error.h" 38 #include "qapi/visitor.h" 39 #include "qemu/module.h" 40 41 /**************************************************************************** 42 * Q35 host 43 */ 44 45 #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 46 47 static void q35_host_realize(DeviceState *dev, Error **errp) 48 { 49 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 50 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 51 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 52 53 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 54 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 55 56 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 57 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 58 59 /* register q35 0xcf8 port as coalesced pio */ 60 memory_region_set_flush_coalesced(&pci->data_mem); 61 memory_region_add_coalescing(&pci->conf_mem, 0, 4); 62 63 pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 64 s->mch.pci_address_space, 65 s->mch.address_space_io, 66 0, TYPE_PCIE_BUS); 67 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 68 qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); 69 } 70 71 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 72 PCIBus *rootbus) 73 { 74 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 75 76 /* For backwards compat with old device paths */ 77 if (s->mch.short_root_bus) { 78 return "0000"; 79 } 80 return "0000:00"; 81 } 82 83 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 84 const char *name, void *opaque, 85 Error **errp) 86 { 87 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 88 uint64_t val64; 89 uint32_t value; 90 91 val64 = range_is_empty(&s->mch.pci_hole) 92 ? 0 : range_lob(&s->mch.pci_hole); 93 value = val64; 94 assert(value == val64); 95 visit_type_uint32(v, name, &value, errp); 96 } 97 98 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 99 const char *name, void *opaque, 100 Error **errp) 101 { 102 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 103 uint64_t val64; 104 uint32_t value; 105 106 val64 = range_is_empty(&s->mch.pci_hole) 107 ? 0 : range_upb(&s->mch.pci_hole) + 1; 108 value = val64; 109 assert(value == val64); 110 visit_type_uint32(v, name, &value, errp); 111 } 112 113 /* 114 * The 64bit PCI hole start is set by the Guest firmware 115 * as the address of the first 64bit PCI MEM resource. 116 * If no PCI device has resources on the 64bit area, 117 * the 64bit PCI hole will start after "over 4G RAM" and the 118 * reserved space for memory hotplug if any. 119 */ 120 static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 121 { 122 PCIHostState *h = PCI_HOST_BRIDGE(obj); 123 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 124 Range w64; 125 uint64_t value; 126 127 pci_bus_get_w64_range(h->bus, &w64); 128 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 129 if (!value && s->pci_hole64_fix) { 130 value = pc_pci_hole64_start(); 131 } 132 return value; 133 } 134 135 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 136 const char *name, void *opaque, 137 Error **errp) 138 { 139 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 140 141 visit_type_uint64(v, name, &hole64_start, errp); 142 } 143 144 /* 145 * The 64bit PCI hole end is set by the Guest firmware 146 * as the address of the last 64bit PCI MEM resource. 147 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 148 * that can be configured by the user. 149 */ 150 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 151 const char *name, void *opaque, 152 Error **errp) 153 { 154 PCIHostState *h = PCI_HOST_BRIDGE(obj); 155 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 156 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 157 Range w64; 158 uint64_t value, hole64_end; 159 160 pci_bus_get_w64_range(h->bus, &w64); 161 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 162 hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 163 if (s->pci_hole64_fix && value < hole64_end) { 164 value = hole64_end; 165 } 166 visit_type_uint64(v, name, &value, errp); 167 } 168 169 /* 170 * NOTE: setting defaults for the mch.* fields in this table 171 * doesn't work, because mch is a separate QOM object that is 172 * zeroed by the object_initialize(&s->mch, ...) call inside 173 * q35_host_initfn(). The default values for those 174 * properties need to be initialized manually by 175 * q35_host_initfn() after the object_initialize() call. 176 */ 177 static Property q35_host_props[] = { 178 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 179 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 180 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 181 mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 182 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 183 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 184 mch.below_4g_mem_size, 0), 185 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 186 mch.above_4g_mem_size, 0), 187 DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 188 DEFINE_PROP_END_OF_LIST(), 189 }; 190 191 static void q35_host_class_init(ObjectClass *klass, void *data) 192 { 193 DeviceClass *dc = DEVICE_CLASS(klass); 194 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 195 196 hc->root_bus_path = q35_host_root_bus_path; 197 dc->realize = q35_host_realize; 198 device_class_set_props(dc, q35_host_props); 199 /* Reason: needs to be wired up by pc_q35_init */ 200 dc->user_creatable = false; 201 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 202 dc->fw_name = "pci"; 203 } 204 205 static void q35_host_initfn(Object *obj) 206 { 207 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 208 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 209 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj); 210 211 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 212 "pci-conf-idx", 4); 213 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 214 "pci-conf-data", 4); 215 216 object_initialize_child(OBJECT(s), "mch", &s->mch, TYPE_MCH_PCI_DEVICE); 217 qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 218 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 219 /* mch's object_initialize resets the default value, set it again */ 220 qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 221 Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 222 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 223 q35_host_get_pci_hole_start, 224 NULL, NULL, NULL); 225 226 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 227 q35_host_get_pci_hole_end, 228 NULL, NULL, NULL); 229 230 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 231 q35_host_get_pci_hole64_start, 232 NULL, NULL, NULL); 233 234 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 235 q35_host_get_pci_hole64_end, 236 NULL, NULL, NULL); 237 238 object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, 239 &pehb->size, OBJ_PROP_FLAG_READ); 240 241 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 242 (Object **) &s->mch.ram_memory, 243 qdev_prop_allow_set_link_before_realize, 0); 244 245 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 246 (Object **) &s->mch.pci_address_space, 247 qdev_prop_allow_set_link_before_realize, 0); 248 249 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 250 (Object **) &s->mch.system_memory, 251 qdev_prop_allow_set_link_before_realize, 0); 252 253 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 254 (Object **) &s->mch.address_space_io, 255 qdev_prop_allow_set_link_before_realize, 0); 256 } 257 258 static const TypeInfo q35_host_info = { 259 .name = TYPE_Q35_HOST_DEVICE, 260 .parent = TYPE_PCIE_HOST_BRIDGE, 261 .instance_size = sizeof(Q35PCIHost), 262 .instance_init = q35_host_initfn, 263 .class_init = q35_host_class_init, 264 }; 265 266 /**************************************************************************** 267 * MCH D0:F0 268 */ 269 270 static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) 271 { 272 return 0xffffffff; 273 } 274 275 static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, 276 unsigned width) 277 { 278 /* nothing */ 279 } 280 281 static const MemoryRegionOps blackhole_ops = { 282 .read = blackhole_read, 283 .write = blackhole_write, 284 .endianness = DEVICE_NATIVE_ENDIAN, 285 .valid.min_access_size = 1, 286 .valid.max_access_size = 4, 287 .impl.min_access_size = 4, 288 .impl.max_access_size = 4, 289 .endianness = DEVICE_LITTLE_ENDIAN, 290 }; 291 292 /* PCIe MMCFG */ 293 static void mch_update_pciexbar(MCHPCIState *mch) 294 { 295 PCIDevice *pci_dev = PCI_DEVICE(mch); 296 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 297 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 298 299 uint64_t pciexbar; 300 int enable; 301 uint64_t addr; 302 uint64_t addr_mask; 303 uint32_t length; 304 305 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 306 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 307 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 308 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 309 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 310 length = 256 * 1024 * 1024; 311 break; 312 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 313 length = 128 * 1024 * 1024; 314 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 315 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 316 break; 317 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 318 length = 64 * 1024 * 1024; 319 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 320 break; 321 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 322 qemu_log_mask(LOG_GUEST_ERROR, "Q35: Reserved PCIEXBAR LENGTH\n"); 323 return; 324 default: 325 abort(); 326 } 327 addr = pciexbar & addr_mask; 328 pcie_host_mmcfg_update(pehb, enable, addr, length); 329 } 330 331 /* PAM */ 332 static void mch_update_pam(MCHPCIState *mch) 333 { 334 PCIDevice *pd = PCI_DEVICE(mch); 335 int i; 336 337 memory_region_transaction_begin(); 338 for (i = 0; i < 13; i++) { 339 pam_update(&mch->pam_regions[i], i, 340 pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 341 } 342 memory_region_transaction_commit(); 343 } 344 345 /* SMRAM */ 346 static void mch_update_smram(MCHPCIState *mch) 347 { 348 PCIDevice *pd = PCI_DEVICE(mch); 349 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 350 uint32_t tseg_size; 351 352 /* implement SMRAM.D_LCK */ 353 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 354 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 355 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 356 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 357 } 358 359 memory_region_transaction_begin(); 360 361 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 362 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 363 memory_region_set_enabled(&mch->smram_region, h_smrame); 364 /* Show high SMRAM if H_SMRAME = 1 */ 365 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 366 } else { 367 /* Hide high SMRAM and low SMRAM */ 368 memory_region_set_enabled(&mch->smram_region, true); 369 memory_region_set_enabled(&mch->open_high_smram, false); 370 } 371 372 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 373 memory_region_set_enabled(&mch->low_smram, !h_smrame); 374 memory_region_set_enabled(&mch->high_smram, h_smrame); 375 } else { 376 memory_region_set_enabled(&mch->low_smram, false); 377 memory_region_set_enabled(&mch->high_smram, false); 378 } 379 380 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 381 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 382 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 383 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 384 tseg_size = 1024 * 1024; 385 break; 386 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 387 tseg_size = 1024 * 1024 * 2; 388 break; 389 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 390 tseg_size = 1024 * 1024 * 8; 391 break; 392 default: 393 tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 394 break; 395 } 396 } else { 397 tseg_size = 0; 398 } 399 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 400 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 401 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 402 memory_region_add_subregion_overlap(mch->system_memory, 403 mch->below_4g_mem_size - tseg_size, 404 &mch->tseg_blackhole, 1); 405 406 memory_region_set_enabled(&mch->tseg_window, tseg_size); 407 memory_region_set_size(&mch->tseg_window, tseg_size); 408 memory_region_set_address(&mch->tseg_window, 409 mch->below_4g_mem_size - tseg_size); 410 memory_region_set_alias_offset(&mch->tseg_window, 411 mch->below_4g_mem_size - tseg_size); 412 413 memory_region_transaction_commit(); 414 } 415 416 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 417 { 418 PCIDevice *pd = PCI_DEVICE(mch); 419 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 420 421 if (mch->ext_tseg_mbytes > 0 && 422 pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 423 pci_set_word(reg, mch->ext_tseg_mbytes); 424 } 425 } 426 427 static void mch_update_smbase_smram(MCHPCIState *mch) 428 { 429 PCIDevice *pd = PCI_DEVICE(mch); 430 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE; 431 bool lck; 432 433 if (!mch->has_smram_at_smbase) { 434 return; 435 } 436 437 if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) { 438 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 439 MCH_HOST_BRIDGE_F_SMBASE_LCK; 440 *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; 441 return; 442 } 443 444 /* 445 * default/reset state, discard written value 446 * which will disable SMRAM balackhole at SMBASE 447 */ 448 if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { 449 *reg = 0x00; 450 } 451 452 memory_region_transaction_begin(); 453 if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { 454 /* disable all writes */ 455 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= 456 ~MCH_HOST_BRIDGE_F_SMBASE_LCK; 457 *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK; 458 lck = true; 459 } else { 460 lck = false; 461 } 462 memory_region_set_enabled(&mch->smbase_blackhole, lck); 463 memory_region_set_enabled(&mch->smbase_window, lck); 464 memory_region_transaction_commit(); 465 } 466 467 static void mch_write_config(PCIDevice *d, 468 uint32_t address, uint32_t val, int len) 469 { 470 MCHPCIState *mch = MCH_PCI_DEVICE(d); 471 472 pci_default_write_config(d, address, val, len); 473 474 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 475 MCH_HOST_BRIDGE_PAM_SIZE)) { 476 mch_update_pam(mch); 477 } 478 479 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 480 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 481 mch_update_pciexbar(mch); 482 } 483 484 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 485 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 486 mch_update_smram(mch); 487 } 488 489 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 490 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 491 mch_update_ext_tseg_mbytes(mch); 492 } 493 494 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { 495 mch_update_smbase_smram(mch); 496 } 497 } 498 499 static void mch_update(MCHPCIState *mch) 500 { 501 mch_update_pciexbar(mch); 502 mch_update_pam(mch); 503 mch_update_smram(mch); 504 mch_update_ext_tseg_mbytes(mch); 505 mch_update_smbase_smram(mch); 506 507 /* 508 * pci hole goes from end-of-low-ram to io-apic. 509 * mmconfig will be excluded by the dsdt builder. 510 */ 511 range_set_bounds(&mch->pci_hole, 512 mch->below_4g_mem_size, 513 IO_APIC_DEFAULT_ADDRESS - 1); 514 } 515 516 static int mch_post_load(void *opaque, int version_id) 517 { 518 MCHPCIState *mch = opaque; 519 mch_update(mch); 520 return 0; 521 } 522 523 static const VMStateDescription vmstate_mch = { 524 .name = "mch", 525 .version_id = 1, 526 .minimum_version_id = 1, 527 .post_load = mch_post_load, 528 .fields = (VMStateField[]) { 529 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 530 /* Used to be smm_enabled, which was basically always zero because 531 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 532 */ 533 VMSTATE_UNUSED(1), 534 VMSTATE_END_OF_LIST() 535 } 536 }; 537 538 static void mch_reset(DeviceState *qdev) 539 { 540 PCIDevice *d = PCI_DEVICE(qdev); 541 MCHPCIState *mch = MCH_PCI_DEVICE(d); 542 543 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 544 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 545 546 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 547 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 548 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 549 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 550 551 if (mch->ext_tseg_mbytes > 0) { 552 pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 553 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 554 } 555 556 d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; 557 d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; 558 559 mch_update(mch); 560 } 561 562 static void mch_realize(PCIDevice *d, Error **errp) 563 { 564 int i; 565 MCHPCIState *mch = MCH_PCI_DEVICE(d); 566 567 if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 568 error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 569 mch->ext_tseg_mbytes); 570 return; 571 } 572 573 /* setup pci memory mapping */ 574 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 575 mch->pci_address_space); 576 577 /* if *disabled* show SMRAM to all CPUs */ 578 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 579 mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 580 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 581 memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 582 &mch->smram_region, 1); 583 memory_region_set_enabled(&mch->smram_region, true); 584 585 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 586 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 587 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 588 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 589 &mch->open_high_smram, 1); 590 memory_region_set_enabled(&mch->open_high_smram, false); 591 592 /* smram, as seen by SMM CPUs */ 593 memory_region_init(&mch->smram, OBJECT(mch), "smram", 4 * GiB); 594 memory_region_set_enabled(&mch->smram, true); 595 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 596 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 597 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 598 memory_region_set_enabled(&mch->low_smram, true); 599 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 600 &mch->low_smram); 601 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 602 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 603 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 604 memory_region_set_enabled(&mch->high_smram, true); 605 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 606 607 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 608 &blackhole_ops, NULL, 609 "tseg-blackhole", 0); 610 memory_region_set_enabled(&mch->tseg_blackhole, false); 611 memory_region_add_subregion_overlap(mch->system_memory, 612 mch->below_4g_mem_size, 613 &mch->tseg_blackhole, 1); 614 615 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 616 mch->ram_memory, mch->below_4g_mem_size, 0); 617 memory_region_set_enabled(&mch->tseg_window, false); 618 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 619 &mch->tseg_window); 620 621 /* 622 * This is not what hardware does, so it's QEMU specific hack. 623 * See commit message for details. 624 */ 625 memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, 626 NULL, "smbase-blackhole", 627 MCH_HOST_BRIDGE_SMBASE_SIZE); 628 memory_region_set_enabled(&mch->smbase_blackhole, false); 629 memory_region_add_subregion_overlap(mch->system_memory, 630 MCH_HOST_BRIDGE_SMBASE_ADDR, 631 &mch->smbase_blackhole, 1); 632 633 memory_region_init_alias(&mch->smbase_window, OBJECT(mch), 634 "smbase-window", mch->ram_memory, 635 MCH_HOST_BRIDGE_SMBASE_ADDR, 636 MCH_HOST_BRIDGE_SMBASE_SIZE); 637 memory_region_set_enabled(&mch->smbase_window, false); 638 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, 639 &mch->smbase_window); 640 641 object_property_add_const_link(qdev_get_machine(), "smram", 642 OBJECT(&mch->smram)); 643 644 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 645 mch->pci_address_space, &mch->pam_regions[0], 646 PAM_BIOS_BASE, PAM_BIOS_SIZE); 647 for (i = 0; i < ARRAY_SIZE(mch->pam_regions) - 1; ++i) { 648 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 649 mch->pci_address_space, &mch->pam_regions[i+1], 650 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 651 } 652 } 653 654 uint64_t mch_mcfg_base(void) 655 { 656 bool ambiguous; 657 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 658 if (!o) { 659 return 0; 660 } 661 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 662 } 663 664 static Property mch_props[] = { 665 DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 666 16), 667 DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), 668 DEFINE_PROP_END_OF_LIST(), 669 }; 670 671 static void mch_class_init(ObjectClass *klass, void *data) 672 { 673 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 674 DeviceClass *dc = DEVICE_CLASS(klass); 675 676 k->realize = mch_realize; 677 k->config_write = mch_write_config; 678 dc->reset = mch_reset; 679 device_class_set_props(dc, mch_props); 680 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 681 dc->desc = "Host bridge"; 682 dc->vmsd = &vmstate_mch; 683 k->vendor_id = PCI_VENDOR_ID_INTEL; 684 /* 685 * The 'q35' machine type implements an Intel Series 3 chipset, 686 * of which there are several variants. The key difference between 687 * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 688 * the latter has an integrated graphics adapter. QEMU does not 689 * implement integrated graphics, so uses the PCI ID for the 82P35 690 * chipset. 691 */ 692 k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 693 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 694 k->class_id = PCI_CLASS_BRIDGE_HOST; 695 /* 696 * PCI-facing part of the host bridge, not usable without the 697 * host-facing part, which can't be device_add'ed, yet. 698 */ 699 dc->user_creatable = false; 700 } 701 702 static const TypeInfo mch_info = { 703 .name = TYPE_MCH_PCI_DEVICE, 704 .parent = TYPE_PCI_DEVICE, 705 .instance_size = sizeof(MCHPCIState), 706 .class_init = mch_class_init, 707 .interfaces = (InterfaceInfo[]) { 708 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 709 { }, 710 }, 711 }; 712 713 static void q35_register(void) 714 { 715 type_register_static(&mch_info); 716 type_register_static(&q35_host_info); 717 } 718 719 type_init(q35_register); 720