1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "hw/hw.h" 33 #include "hw/pci-host/q35.h" 34 #include "qapi/error.h" 35 #include "qapi/visitor.h" 36 #include "qemu/module.h" 37 38 /**************************************************************************** 39 * Q35 host 40 */ 41 42 #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 43 44 static void q35_host_realize(DeviceState *dev, Error **errp) 45 { 46 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 47 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 48 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 49 50 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 51 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 52 53 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 54 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 55 56 /* register q35 0xcf8 port as coalesced pio */ 57 memory_region_set_flush_coalesced(&pci->data_mem); 58 memory_region_add_coalescing(&pci->conf_mem, 0, 4); 59 60 pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 61 s->mch.pci_address_space, 62 s->mch.address_space_io, 63 0, TYPE_PCIE_BUS); 64 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 65 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 66 qdev_init_nofail(DEVICE(&s->mch)); 67 } 68 69 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 70 PCIBus *rootbus) 71 { 72 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 73 74 /* For backwards compat with old device paths */ 75 if (s->mch.short_root_bus) { 76 return "0000"; 77 } 78 return "0000:00"; 79 } 80 81 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 82 const char *name, void *opaque, 83 Error **errp) 84 { 85 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 86 uint64_t val64; 87 uint32_t value; 88 89 val64 = range_is_empty(&s->mch.pci_hole) 90 ? 0 : range_lob(&s->mch.pci_hole); 91 value = val64; 92 assert(value == val64); 93 visit_type_uint32(v, name, &value, errp); 94 } 95 96 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 97 const char *name, void *opaque, 98 Error **errp) 99 { 100 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 101 uint64_t val64; 102 uint32_t value; 103 104 val64 = range_is_empty(&s->mch.pci_hole) 105 ? 0 : range_upb(&s->mch.pci_hole) + 1; 106 value = val64; 107 assert(value == val64); 108 visit_type_uint32(v, name, &value, errp); 109 } 110 111 /* 112 * The 64bit PCI hole start is set by the Guest firmware 113 * as the address of the first 64bit PCI MEM resource. 114 * If no PCI device has resources on the 64bit area, 115 * the 64bit PCI hole will start after "over 4G RAM" and the 116 * reserved space for memory hotplug if any. 117 */ 118 static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 119 { 120 PCIHostState *h = PCI_HOST_BRIDGE(obj); 121 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 122 Range w64; 123 uint64_t value; 124 125 pci_bus_get_w64_range(h->bus, &w64); 126 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 127 if (!value && s->pci_hole64_fix) { 128 value = pc_pci_hole64_start(); 129 } 130 return value; 131 } 132 133 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 134 const char *name, void *opaque, 135 Error **errp) 136 { 137 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 138 139 visit_type_uint64(v, name, &hole64_start, errp); 140 } 141 142 /* 143 * The 64bit PCI hole end is set by the Guest firmware 144 * as the address of the last 64bit PCI MEM resource. 145 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 146 * that can be configured by the user. 147 */ 148 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 149 const char *name, void *opaque, 150 Error **errp) 151 { 152 PCIHostState *h = PCI_HOST_BRIDGE(obj); 153 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 154 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 155 Range w64; 156 uint64_t value, hole64_end; 157 158 pci_bus_get_w64_range(h->bus, &w64); 159 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 160 hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 161 if (s->pci_hole64_fix && value < hole64_end) { 162 value = hole64_end; 163 } 164 visit_type_uint64(v, name, &value, errp); 165 } 166 167 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 168 void *opaque, Error **errp) 169 { 170 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 171 172 visit_type_uint64(v, name, &e->size, errp); 173 } 174 175 /* 176 * NOTE: setting defaults for the mch.* fields in this table 177 * doesn't work, because mch is a separate QOM object that is 178 * zeroed by the object_initialize(&s->mch, ...) call inside 179 * q35_host_initfn(). The default values for those 180 * properties need to be initialized manually by 181 * q35_host_initfn() after the object_initialize() call. 182 */ 183 static Property q35_host_props[] = { 184 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 185 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 186 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 187 mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 188 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 189 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 190 mch.below_4g_mem_size, 0), 191 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 192 mch.above_4g_mem_size, 0), 193 DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 194 DEFINE_PROP_END_OF_LIST(), 195 }; 196 197 static void q35_host_class_init(ObjectClass *klass, void *data) 198 { 199 DeviceClass *dc = DEVICE_CLASS(klass); 200 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 201 202 hc->root_bus_path = q35_host_root_bus_path; 203 dc->realize = q35_host_realize; 204 dc->props = q35_host_props; 205 /* Reason: needs to be wired up by pc_q35_init */ 206 dc->user_creatable = false; 207 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 208 dc->fw_name = "pci"; 209 } 210 211 static void q35_host_initfn(Object *obj) 212 { 213 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 214 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 215 216 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 217 "pci-conf-idx", 4); 218 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 219 "pci-conf-data", 4); 220 221 object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch), 222 TYPE_MCH_PCI_DEVICE, &error_abort, NULL); 223 qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 224 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 225 /* mch's object_initialize resets the default value, set it again */ 226 qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 227 Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 228 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 229 q35_host_get_pci_hole_start, 230 NULL, NULL, NULL, NULL); 231 232 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 233 q35_host_get_pci_hole_end, 234 NULL, NULL, NULL, NULL); 235 236 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 237 q35_host_get_pci_hole64_start, 238 NULL, NULL, NULL, NULL); 239 240 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 241 q35_host_get_pci_hole64_end, 242 NULL, NULL, NULL, NULL); 243 244 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "uint64", 245 q35_host_get_mmcfg_size, 246 NULL, NULL, NULL, NULL); 247 248 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 249 (Object **) &s->mch.ram_memory, 250 qdev_prop_allow_set_link_before_realize, 0, NULL); 251 252 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 253 (Object **) &s->mch.pci_address_space, 254 qdev_prop_allow_set_link_before_realize, 0, NULL); 255 256 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 257 (Object **) &s->mch.system_memory, 258 qdev_prop_allow_set_link_before_realize, 0, NULL); 259 260 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 261 (Object **) &s->mch.address_space_io, 262 qdev_prop_allow_set_link_before_realize, 0, NULL); 263 } 264 265 static const TypeInfo q35_host_info = { 266 .name = TYPE_Q35_HOST_DEVICE, 267 .parent = TYPE_PCIE_HOST_BRIDGE, 268 .instance_size = sizeof(Q35PCIHost), 269 .instance_init = q35_host_initfn, 270 .class_init = q35_host_class_init, 271 }; 272 273 /**************************************************************************** 274 * MCH D0:F0 275 */ 276 277 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 278 { 279 return 0xffffffff; 280 } 281 282 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 283 unsigned width) 284 { 285 /* nothing */ 286 } 287 288 static const MemoryRegionOps tseg_blackhole_ops = { 289 .read = tseg_blackhole_read, 290 .write = tseg_blackhole_write, 291 .endianness = DEVICE_NATIVE_ENDIAN, 292 .valid.min_access_size = 1, 293 .valid.max_access_size = 4, 294 .impl.min_access_size = 4, 295 .impl.max_access_size = 4, 296 .endianness = DEVICE_LITTLE_ENDIAN, 297 }; 298 299 /* PCIe MMCFG */ 300 static void mch_update_pciexbar(MCHPCIState *mch) 301 { 302 PCIDevice *pci_dev = PCI_DEVICE(mch); 303 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 304 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 305 306 uint64_t pciexbar; 307 int enable; 308 uint64_t addr; 309 uint64_t addr_mask; 310 uint32_t length; 311 312 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 313 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 314 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 315 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 316 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 317 length = 256 * 1024 * 1024; 318 break; 319 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 320 length = 128 * 1024 * 1024; 321 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 322 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 323 break; 324 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 325 length = 64 * 1024 * 1024; 326 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 327 break; 328 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 329 default: 330 abort(); 331 } 332 addr = pciexbar & addr_mask; 333 pcie_host_mmcfg_update(pehb, enable, addr, length); 334 } 335 336 /* PAM */ 337 static void mch_update_pam(MCHPCIState *mch) 338 { 339 PCIDevice *pd = PCI_DEVICE(mch); 340 int i; 341 342 memory_region_transaction_begin(); 343 for (i = 0; i < 13; i++) { 344 pam_update(&mch->pam_regions[i], i, 345 pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 346 } 347 memory_region_transaction_commit(); 348 } 349 350 /* SMRAM */ 351 static void mch_update_smram(MCHPCIState *mch) 352 { 353 PCIDevice *pd = PCI_DEVICE(mch); 354 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 355 uint32_t tseg_size; 356 357 /* implement SMRAM.D_LCK */ 358 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 359 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 360 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 361 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 362 } 363 364 memory_region_transaction_begin(); 365 366 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 367 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 368 memory_region_set_enabled(&mch->smram_region, h_smrame); 369 /* Show high SMRAM if H_SMRAME = 1 */ 370 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 371 } else { 372 /* Hide high SMRAM and low SMRAM */ 373 memory_region_set_enabled(&mch->smram_region, true); 374 memory_region_set_enabled(&mch->open_high_smram, false); 375 } 376 377 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 378 memory_region_set_enabled(&mch->low_smram, !h_smrame); 379 memory_region_set_enabled(&mch->high_smram, h_smrame); 380 } else { 381 memory_region_set_enabled(&mch->low_smram, false); 382 memory_region_set_enabled(&mch->high_smram, false); 383 } 384 385 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 386 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 387 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 388 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 389 tseg_size = 1024 * 1024; 390 break; 391 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 392 tseg_size = 1024 * 1024 * 2; 393 break; 394 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 395 tseg_size = 1024 * 1024 * 8; 396 break; 397 default: 398 tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 399 break; 400 } 401 } else { 402 tseg_size = 0; 403 } 404 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 405 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 406 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 407 memory_region_add_subregion_overlap(mch->system_memory, 408 mch->below_4g_mem_size - tseg_size, 409 &mch->tseg_blackhole, 1); 410 411 memory_region_set_enabled(&mch->tseg_window, tseg_size); 412 memory_region_set_size(&mch->tseg_window, tseg_size); 413 memory_region_set_address(&mch->tseg_window, 414 mch->below_4g_mem_size - tseg_size); 415 memory_region_set_alias_offset(&mch->tseg_window, 416 mch->below_4g_mem_size - tseg_size); 417 418 memory_region_transaction_commit(); 419 } 420 421 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 422 { 423 PCIDevice *pd = PCI_DEVICE(mch); 424 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 425 426 if (mch->ext_tseg_mbytes > 0 && 427 pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 428 pci_set_word(reg, mch->ext_tseg_mbytes); 429 } 430 } 431 432 static void mch_write_config(PCIDevice *d, 433 uint32_t address, uint32_t val, int len) 434 { 435 MCHPCIState *mch = MCH_PCI_DEVICE(d); 436 437 pci_default_write_config(d, address, val, len); 438 439 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 440 MCH_HOST_BRIDGE_PAM_SIZE)) { 441 mch_update_pam(mch); 442 } 443 444 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 445 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 446 mch_update_pciexbar(mch); 447 } 448 449 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 450 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 451 mch_update_smram(mch); 452 } 453 454 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 455 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 456 mch_update_ext_tseg_mbytes(mch); 457 } 458 } 459 460 static void mch_update(MCHPCIState *mch) 461 { 462 mch_update_pciexbar(mch); 463 mch_update_pam(mch); 464 mch_update_smram(mch); 465 mch_update_ext_tseg_mbytes(mch); 466 467 /* 468 * pci hole goes from end-of-low-ram to io-apic. 469 * mmconfig will be excluded by the dsdt builder. 470 */ 471 range_set_bounds(&mch->pci_hole, 472 mch->below_4g_mem_size, 473 IO_APIC_DEFAULT_ADDRESS - 1); 474 } 475 476 static int mch_post_load(void *opaque, int version_id) 477 { 478 MCHPCIState *mch = opaque; 479 mch_update(mch); 480 return 0; 481 } 482 483 static const VMStateDescription vmstate_mch = { 484 .name = "mch", 485 .version_id = 1, 486 .minimum_version_id = 1, 487 .post_load = mch_post_load, 488 .fields = (VMStateField[]) { 489 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 490 /* Used to be smm_enabled, which was basically always zero because 491 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 492 */ 493 VMSTATE_UNUSED(1), 494 VMSTATE_END_OF_LIST() 495 } 496 }; 497 498 static void mch_reset(DeviceState *qdev) 499 { 500 PCIDevice *d = PCI_DEVICE(qdev); 501 MCHPCIState *mch = MCH_PCI_DEVICE(d); 502 503 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 504 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 505 506 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 507 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 508 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 509 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 510 511 if (mch->ext_tseg_mbytes > 0) { 512 pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 513 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 514 } 515 516 mch_update(mch); 517 } 518 519 static void mch_realize(PCIDevice *d, Error **errp) 520 { 521 int i; 522 MCHPCIState *mch = MCH_PCI_DEVICE(d); 523 524 if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 525 error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 526 mch->ext_tseg_mbytes); 527 return; 528 } 529 530 /* setup pci memory mapping */ 531 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 532 mch->pci_address_space); 533 534 /* if *disabled* show SMRAM to all CPUs */ 535 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 536 mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 537 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 538 memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 539 &mch->smram_region, 1); 540 memory_region_set_enabled(&mch->smram_region, true); 541 542 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 543 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 544 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 545 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 546 &mch->open_high_smram, 1); 547 memory_region_set_enabled(&mch->open_high_smram, false); 548 549 /* smram, as seen by SMM CPUs */ 550 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 551 memory_region_set_enabled(&mch->smram, true); 552 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 553 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 554 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 555 memory_region_set_enabled(&mch->low_smram, true); 556 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 557 &mch->low_smram); 558 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 559 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 560 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 561 memory_region_set_enabled(&mch->high_smram, true); 562 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 563 564 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 565 &tseg_blackhole_ops, NULL, 566 "tseg-blackhole", 0); 567 memory_region_set_enabled(&mch->tseg_blackhole, false); 568 memory_region_add_subregion_overlap(mch->system_memory, 569 mch->below_4g_mem_size, 570 &mch->tseg_blackhole, 1); 571 572 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 573 mch->ram_memory, mch->below_4g_mem_size, 0); 574 memory_region_set_enabled(&mch->tseg_window, false); 575 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 576 &mch->tseg_window); 577 object_property_add_const_link(qdev_get_machine(), "smram", 578 OBJECT(&mch->smram), &error_abort); 579 580 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 581 mch->pci_address_space, &mch->pam_regions[0], 582 PAM_BIOS_BASE, PAM_BIOS_SIZE); 583 for (i = 0; i < 12; ++i) { 584 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 585 mch->pci_address_space, &mch->pam_regions[i+1], 586 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 587 } 588 } 589 590 uint64_t mch_mcfg_base(void) 591 { 592 bool ambiguous; 593 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 594 if (!o) { 595 return 0; 596 } 597 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 598 } 599 600 static Property mch_props[] = { 601 DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 602 16), 603 DEFINE_PROP_END_OF_LIST(), 604 }; 605 606 static void mch_class_init(ObjectClass *klass, void *data) 607 { 608 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 609 DeviceClass *dc = DEVICE_CLASS(klass); 610 611 k->realize = mch_realize; 612 k->config_write = mch_write_config; 613 dc->reset = mch_reset; 614 dc->props = mch_props; 615 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 616 dc->desc = "Host bridge"; 617 dc->vmsd = &vmstate_mch; 618 k->vendor_id = PCI_VENDOR_ID_INTEL; 619 /* 620 * The 'q35' machine type implements an Intel Series 3 chipset, 621 * of which there are several variants. The key difference between 622 * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 623 * the latter has an integrated graphics adapter. QEMU does not 624 * implement integrated graphics, so uses the PCI ID for the 82P35 625 * chipset. 626 */ 627 k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 628 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 629 k->class_id = PCI_CLASS_BRIDGE_HOST; 630 /* 631 * PCI-facing part of the host bridge, not usable without the 632 * host-facing part, which can't be device_add'ed, yet. 633 */ 634 dc->user_creatable = false; 635 } 636 637 static const TypeInfo mch_info = { 638 .name = TYPE_MCH_PCI_DEVICE, 639 .parent = TYPE_PCI_DEVICE, 640 .instance_size = sizeof(MCHPCIState), 641 .class_init = mch_class_init, 642 .interfaces = (InterfaceInfo[]) { 643 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 644 { }, 645 }, 646 }; 647 648 static void q35_register(void) 649 { 650 type_register_static(&mch_info); 651 type_register_static(&q35_host_info); 652 } 653 654 type_init(q35_register); 655