1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/pci-host/q35.h" 33 #include "qapi/error.h" 34 #include "qapi/visitor.h" 35 36 /**************************************************************************** 37 * Q35 host 38 */ 39 40 static void q35_host_realize(DeviceState *dev, Error **errp) 41 { 42 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 43 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 44 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 45 46 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 47 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 48 49 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 50 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 51 52 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 53 s->mch.pci_address_space, s->mch.address_space_io, 54 0, TYPE_PCIE_BUS); 55 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 56 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 57 qdev_init_nofail(DEVICE(&s->mch)); 58 } 59 60 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 61 PCIBus *rootbus) 62 { 63 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 64 65 /* For backwards compat with old device paths */ 66 if (s->mch.short_root_bus) { 67 return "0000"; 68 } 69 return "0000:00"; 70 } 71 72 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 73 const char *name, void *opaque, 74 Error **errp) 75 { 76 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 77 uint64_t val64; 78 uint32_t value; 79 80 val64 = range_is_empty(&s->mch.pci_hole) 81 ? 0 : range_lob(&s->mch.pci_hole); 82 value = val64; 83 assert(value == val64); 84 visit_type_uint32(v, name, &value, errp); 85 } 86 87 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 88 const char *name, void *opaque, 89 Error **errp) 90 { 91 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 92 uint64_t val64; 93 uint32_t value; 94 95 val64 = range_is_empty(&s->mch.pci_hole) 96 ? 0 : range_upb(&s->mch.pci_hole) + 1; 97 value = val64; 98 assert(value == val64); 99 visit_type_uint32(v, name, &value, errp); 100 } 101 102 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 103 const char *name, void *opaque, 104 Error **errp) 105 { 106 PCIHostState *h = PCI_HOST_BRIDGE(obj); 107 Range w64; 108 uint64_t value; 109 110 pci_bus_get_w64_range(h->bus, &w64); 111 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 112 visit_type_uint64(v, name, &value, errp); 113 } 114 115 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 116 const char *name, void *opaque, 117 Error **errp) 118 { 119 PCIHostState *h = PCI_HOST_BRIDGE(obj); 120 Range w64; 121 uint64_t value; 122 123 pci_bus_get_w64_range(h->bus, &w64); 124 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 125 visit_type_uint64(v, name, &value, errp); 126 } 127 128 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 129 void *opaque, Error **errp) 130 { 131 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 132 uint32_t value = e->size; 133 134 visit_type_uint32(v, name, &value, errp); 135 } 136 137 static Property mch_props[] = { 138 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 139 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 140 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 141 mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 142 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 143 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 144 mch.below_4g_mem_size, 0), 145 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 146 mch.above_4g_mem_size, 0), 147 DEFINE_PROP_END_OF_LIST(), 148 }; 149 150 static void q35_host_class_init(ObjectClass *klass, void *data) 151 { 152 DeviceClass *dc = DEVICE_CLASS(klass); 153 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 154 155 hc->root_bus_path = q35_host_root_bus_path; 156 dc->realize = q35_host_realize; 157 dc->props = mch_props; 158 /* Reason: needs to be wired up by pc_q35_init */ 159 dc->cannot_instantiate_with_device_add_yet = true; 160 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 161 dc->fw_name = "pci"; 162 } 163 164 static void q35_host_initfn(Object *obj) 165 { 166 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 167 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 168 169 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 170 "pci-conf-idx", 4); 171 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 172 "pci-conf-data", 4); 173 174 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 175 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 176 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 177 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 178 179 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 180 q35_host_get_pci_hole_start, 181 NULL, NULL, NULL, NULL); 182 183 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 184 q35_host_get_pci_hole_end, 185 NULL, NULL, NULL, NULL); 186 187 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 188 q35_host_get_pci_hole64_start, 189 NULL, NULL, NULL, NULL); 190 191 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 192 q35_host_get_pci_hole64_end, 193 NULL, NULL, NULL, NULL); 194 195 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", 196 q35_host_get_mmcfg_size, 197 NULL, NULL, NULL, NULL); 198 199 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 200 (Object **) &s->mch.ram_memory, 201 qdev_prop_allow_set_link_before_realize, 0, NULL); 202 203 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 204 (Object **) &s->mch.pci_address_space, 205 qdev_prop_allow_set_link_before_realize, 0, NULL); 206 207 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 208 (Object **) &s->mch.system_memory, 209 qdev_prop_allow_set_link_before_realize, 0, NULL); 210 211 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 212 (Object **) &s->mch.address_space_io, 213 qdev_prop_allow_set_link_before_realize, 0, NULL); 214 215 /* Leave enough space for the biggest MCFG BAR */ 216 /* TODO: this matches current bios behaviour, but 217 * it's not a power of two, which means an MTRR 218 * can't cover it exactly. 219 */ 220 range_set_bounds(&s->mch.pci_hole, 221 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + MCH_HOST_BRIDGE_PCIEXBAR_MAX, 222 IO_APIC_DEFAULT_ADDRESS - 1); 223 } 224 225 static const TypeInfo q35_host_info = { 226 .name = TYPE_Q35_HOST_DEVICE, 227 .parent = TYPE_PCIE_HOST_BRIDGE, 228 .instance_size = sizeof(Q35PCIHost), 229 .instance_init = q35_host_initfn, 230 .class_init = q35_host_class_init, 231 }; 232 233 /**************************************************************************** 234 * MCH D0:F0 235 */ 236 237 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 238 { 239 return 0xffffffff; 240 } 241 242 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 243 unsigned width) 244 { 245 /* nothing */ 246 } 247 248 static const MemoryRegionOps tseg_blackhole_ops = { 249 .read = tseg_blackhole_read, 250 .write = tseg_blackhole_write, 251 .endianness = DEVICE_NATIVE_ENDIAN, 252 .valid.min_access_size = 1, 253 .valid.max_access_size = 4, 254 .impl.min_access_size = 4, 255 .impl.max_access_size = 4, 256 .endianness = DEVICE_LITTLE_ENDIAN, 257 }; 258 259 /* PCIe MMCFG */ 260 static void mch_update_pciexbar(MCHPCIState *mch) 261 { 262 PCIDevice *pci_dev = PCI_DEVICE(mch); 263 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 264 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 265 266 uint64_t pciexbar; 267 int enable; 268 uint64_t addr; 269 uint64_t addr_mask; 270 uint32_t length; 271 272 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 273 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 274 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 275 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 276 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 277 length = 256 * 1024 * 1024; 278 break; 279 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 280 length = 128 * 1024 * 1024; 281 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 282 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 283 break; 284 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 285 length = 64 * 1024 * 1024; 286 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 287 break; 288 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 289 default: 290 abort(); 291 } 292 addr = pciexbar & addr_mask; 293 pcie_host_mmcfg_update(pehb, enable, addr, length); 294 /* Leave enough space for the MCFG BAR */ 295 /* 296 * TODO: this matches current bios behaviour, but it's not a power of two, 297 * which means an MTRR can't cover it exactly. 298 */ 299 if (enable) { 300 range_set_bounds(&mch->pci_hole, 301 addr + length, 302 IO_APIC_DEFAULT_ADDRESS - 1); 303 } else { 304 range_set_bounds(&mch->pci_hole, 305 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT, 306 IO_APIC_DEFAULT_ADDRESS - 1); 307 } 308 } 309 310 /* PAM */ 311 static void mch_update_pam(MCHPCIState *mch) 312 { 313 PCIDevice *pd = PCI_DEVICE(mch); 314 int i; 315 316 memory_region_transaction_begin(); 317 for (i = 0; i < 13; i++) { 318 pam_update(&mch->pam_regions[i], i, 319 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 320 } 321 memory_region_transaction_commit(); 322 } 323 324 /* SMRAM */ 325 static void mch_update_smram(MCHPCIState *mch) 326 { 327 PCIDevice *pd = PCI_DEVICE(mch); 328 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 329 uint32_t tseg_size; 330 331 /* implement SMRAM.D_LCK */ 332 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 333 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 334 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 335 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 336 } 337 338 memory_region_transaction_begin(); 339 340 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 341 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 342 memory_region_set_enabled(&mch->smram_region, h_smrame); 343 /* Show high SMRAM if H_SMRAME = 1 */ 344 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 345 } else { 346 /* Hide high SMRAM and low SMRAM */ 347 memory_region_set_enabled(&mch->smram_region, true); 348 memory_region_set_enabled(&mch->open_high_smram, false); 349 } 350 351 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 352 memory_region_set_enabled(&mch->low_smram, !h_smrame); 353 memory_region_set_enabled(&mch->high_smram, h_smrame); 354 } else { 355 memory_region_set_enabled(&mch->low_smram, false); 356 memory_region_set_enabled(&mch->high_smram, false); 357 } 358 359 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 360 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 361 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 362 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 363 tseg_size = 1024 * 1024; 364 break; 365 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 366 tseg_size = 1024 * 1024 * 2; 367 break; 368 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 369 tseg_size = 1024 * 1024 * 8; 370 break; 371 default: 372 tseg_size = 0; 373 break; 374 } 375 } else { 376 tseg_size = 0; 377 } 378 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 379 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 380 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 381 memory_region_add_subregion_overlap(mch->system_memory, 382 mch->below_4g_mem_size - tseg_size, 383 &mch->tseg_blackhole, 1); 384 385 memory_region_set_enabled(&mch->tseg_window, tseg_size); 386 memory_region_set_size(&mch->tseg_window, tseg_size); 387 memory_region_set_address(&mch->tseg_window, 388 mch->below_4g_mem_size - tseg_size); 389 memory_region_set_alias_offset(&mch->tseg_window, 390 mch->below_4g_mem_size - tseg_size); 391 392 memory_region_transaction_commit(); 393 } 394 395 static void mch_write_config(PCIDevice *d, 396 uint32_t address, uint32_t val, int len) 397 { 398 MCHPCIState *mch = MCH_PCI_DEVICE(d); 399 400 pci_default_write_config(d, address, val, len); 401 402 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 403 MCH_HOST_BRIDGE_PAM_SIZE)) { 404 mch_update_pam(mch); 405 } 406 407 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 408 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 409 mch_update_pciexbar(mch); 410 } 411 412 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 413 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 414 mch_update_smram(mch); 415 } 416 } 417 418 static void mch_update(MCHPCIState *mch) 419 { 420 mch_update_pciexbar(mch); 421 mch_update_pam(mch); 422 mch_update_smram(mch); 423 } 424 425 static int mch_post_load(void *opaque, int version_id) 426 { 427 MCHPCIState *mch = opaque; 428 mch_update(mch); 429 return 0; 430 } 431 432 static const VMStateDescription vmstate_mch = { 433 .name = "mch", 434 .version_id = 1, 435 .minimum_version_id = 1, 436 .post_load = mch_post_load, 437 .fields = (VMStateField[]) { 438 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 439 /* Used to be smm_enabled, which was basically always zero because 440 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 441 */ 442 VMSTATE_UNUSED(1), 443 VMSTATE_END_OF_LIST() 444 } 445 }; 446 447 static void mch_reset(DeviceState *qdev) 448 { 449 PCIDevice *d = PCI_DEVICE(qdev); 450 MCHPCIState *mch = MCH_PCI_DEVICE(d); 451 452 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 453 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 454 455 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 456 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 457 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 458 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 459 460 mch_update(mch); 461 } 462 463 static void mch_realize(PCIDevice *d, Error **errp) 464 { 465 int i; 466 MCHPCIState *mch = MCH_PCI_DEVICE(d); 467 468 /* setup pci memory mapping */ 469 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 470 mch->pci_address_space); 471 472 /* if *disabled* show SMRAM to all CPUs */ 473 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 474 mch->pci_address_space, 0xa0000, 0x20000); 475 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 476 &mch->smram_region, 1); 477 memory_region_set_enabled(&mch->smram_region, true); 478 479 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 480 mch->ram_memory, 0xa0000, 0x20000); 481 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 482 &mch->open_high_smram, 1); 483 memory_region_set_enabled(&mch->open_high_smram, false); 484 485 /* smram, as seen by SMM CPUs */ 486 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 487 memory_region_set_enabled(&mch->smram, true); 488 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 489 mch->ram_memory, 0xa0000, 0x20000); 490 memory_region_set_enabled(&mch->low_smram, true); 491 memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 492 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 493 mch->ram_memory, 0xa0000, 0x20000); 494 memory_region_set_enabled(&mch->high_smram, true); 495 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 496 497 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 498 &tseg_blackhole_ops, NULL, 499 "tseg-blackhole", 0); 500 memory_region_set_enabled(&mch->tseg_blackhole, false); 501 memory_region_add_subregion_overlap(mch->system_memory, 502 mch->below_4g_mem_size, 503 &mch->tseg_blackhole, 1); 504 505 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 506 mch->ram_memory, mch->below_4g_mem_size, 0); 507 memory_region_set_enabled(&mch->tseg_window, false); 508 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 509 &mch->tseg_window); 510 object_property_add_const_link(qdev_get_machine(), "smram", 511 OBJECT(&mch->smram), &error_abort); 512 513 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 514 mch->pci_address_space, &mch->pam_regions[0], 515 PAM_BIOS_BASE, PAM_BIOS_SIZE); 516 for (i = 0; i < 12; ++i) { 517 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 518 mch->pci_address_space, &mch->pam_regions[i+1], 519 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 520 } 521 } 522 523 uint64_t mch_mcfg_base(void) 524 { 525 bool ambiguous; 526 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 527 if (!o) { 528 return 0; 529 } 530 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 531 } 532 533 static void mch_class_init(ObjectClass *klass, void *data) 534 { 535 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 536 DeviceClass *dc = DEVICE_CLASS(klass); 537 538 k->realize = mch_realize; 539 k->config_write = mch_write_config; 540 dc->reset = mch_reset; 541 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 542 dc->desc = "Host bridge"; 543 dc->vmsd = &vmstate_mch; 544 k->vendor_id = PCI_VENDOR_ID_INTEL; 545 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 546 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 547 k->class_id = PCI_CLASS_BRIDGE_HOST; 548 /* 549 * PCI-facing part of the host bridge, not usable without the 550 * host-facing part, which can't be device_add'ed, yet. 551 */ 552 dc->cannot_instantiate_with_device_add_yet = true; 553 } 554 555 static const TypeInfo mch_info = { 556 .name = TYPE_MCH_PCI_DEVICE, 557 .parent = TYPE_PCI_DEVICE, 558 .instance_size = sizeof(MCHPCIState), 559 .class_init = mch_class_init, 560 }; 561 562 static void q35_register(void) 563 { 564 type_register_static(&mch_info); 565 type_register_static(&q35_host_info); 566 } 567 568 type_init(q35_register); 569