1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 31 #include "qemu/osdep.h" 32 #include "hw/i386/pc.h" 33 #include "hw/pci-host/q35.h" 34 #include "hw/qdev-properties.h" 35 #include "migration/vmstate.h" 36 #include "qapi/error.h" 37 #include "qapi/visitor.h" 38 #include "qemu/module.h" 39 40 /**************************************************************************** 41 * Q35 host 42 */ 43 44 #define Q35_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 35) 45 46 static void q35_host_realize(DeviceState *dev, Error **errp) 47 { 48 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 49 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 50 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 51 52 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 53 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 54 55 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 56 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 57 58 /* register q35 0xcf8 port as coalesced pio */ 59 memory_region_set_flush_coalesced(&pci->data_mem); 60 memory_region_add_coalescing(&pci->conf_mem, 0, 4); 61 62 pci->bus = pci_root_bus_new(DEVICE(s), "pcie.0", 63 s->mch.pci_address_space, 64 s->mch.address_space_io, 65 0, TYPE_PCIE_BUS); 66 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 67 qdev_realize(DEVICE(&s->mch), BUS(pci->bus), &error_fatal); 68 } 69 70 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 71 PCIBus *rootbus) 72 { 73 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 74 75 /* For backwards compat with old device paths */ 76 if (s->mch.short_root_bus) { 77 return "0000"; 78 } 79 return "0000:00"; 80 } 81 82 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 83 const char *name, void *opaque, 84 Error **errp) 85 { 86 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 87 uint64_t val64; 88 uint32_t value; 89 90 val64 = range_is_empty(&s->mch.pci_hole) 91 ? 0 : range_lob(&s->mch.pci_hole); 92 value = val64; 93 assert(value == val64); 94 visit_type_uint32(v, name, &value, errp); 95 } 96 97 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 98 const char *name, void *opaque, 99 Error **errp) 100 { 101 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 102 uint64_t val64; 103 uint32_t value; 104 105 val64 = range_is_empty(&s->mch.pci_hole) 106 ? 0 : range_upb(&s->mch.pci_hole) + 1; 107 value = val64; 108 assert(value == val64); 109 visit_type_uint32(v, name, &value, errp); 110 } 111 112 /* 113 * The 64bit PCI hole start is set by the Guest firmware 114 * as the address of the first 64bit PCI MEM resource. 115 * If no PCI device has resources on the 64bit area, 116 * the 64bit PCI hole will start after "over 4G RAM" and the 117 * reserved space for memory hotplug if any. 118 */ 119 static uint64_t q35_host_get_pci_hole64_start_value(Object *obj) 120 { 121 PCIHostState *h = PCI_HOST_BRIDGE(obj); 122 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 123 Range w64; 124 uint64_t value; 125 126 pci_bus_get_w64_range(h->bus, &w64); 127 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 128 if (!value && s->pci_hole64_fix) { 129 value = pc_pci_hole64_start(); 130 } 131 return value; 132 } 133 134 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 135 const char *name, void *opaque, 136 Error **errp) 137 { 138 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 139 140 visit_type_uint64(v, name, &hole64_start, errp); 141 } 142 143 /* 144 * The 64bit PCI hole end is set by the Guest firmware 145 * as the address of the last 64bit PCI MEM resource. 146 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 147 * that can be configured by the user. 148 */ 149 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 150 const char *name, void *opaque, 151 Error **errp) 152 { 153 PCIHostState *h = PCI_HOST_BRIDGE(obj); 154 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 155 uint64_t hole64_start = q35_host_get_pci_hole64_start_value(obj); 156 Range w64; 157 uint64_t value, hole64_end; 158 159 pci_bus_get_w64_range(h->bus, &w64); 160 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 161 hole64_end = ROUND_UP(hole64_start + s->mch.pci_hole64_size, 1ULL << 30); 162 if (s->pci_hole64_fix && value < hole64_end) { 163 value = hole64_end; 164 } 165 visit_type_uint64(v, name, &value, errp); 166 } 167 168 /* 169 * NOTE: setting defaults for the mch.* fields in this table 170 * doesn't work, because mch is a separate QOM object that is 171 * zeroed by the object_initialize(&s->mch, ...) call inside 172 * q35_host_initfn(). The default values for those 173 * properties need to be initialized manually by 174 * q35_host_initfn() after the object_initialize() call. 175 */ 176 static Property q35_host_props[] = { 177 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 178 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 179 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 180 mch.pci_hole64_size, Q35_PCI_HOST_HOLE64_SIZE_DEFAULT), 181 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 182 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 183 mch.below_4g_mem_size, 0), 184 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 185 mch.above_4g_mem_size, 0), 186 DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), 187 DEFINE_PROP_END_OF_LIST(), 188 }; 189 190 static void q35_host_class_init(ObjectClass *klass, void *data) 191 { 192 DeviceClass *dc = DEVICE_CLASS(klass); 193 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 194 195 hc->root_bus_path = q35_host_root_bus_path; 196 dc->realize = q35_host_realize; 197 device_class_set_props(dc, q35_host_props); 198 /* Reason: needs to be wired up by pc_q35_init */ 199 dc->user_creatable = false; 200 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 201 dc->fw_name = "pci"; 202 } 203 204 static void q35_host_initfn(Object *obj) 205 { 206 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 207 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 208 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(obj); 209 210 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 211 "pci-conf-idx", 4); 212 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 213 "pci-conf-data", 4); 214 215 object_initialize_child(OBJECT(s), "mch", &s->mch, sizeof(s->mch), 216 TYPE_MCH_PCI_DEVICE, &error_abort, NULL); 217 qdev_prop_set_int32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 218 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 219 /* mch's object_initialize resets the default value, set it again */ 220 qdev_prop_set_uint64(DEVICE(s), PCI_HOST_PROP_PCI_HOLE64_SIZE, 221 Q35_PCI_HOST_HOLE64_SIZE_DEFAULT); 222 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 223 q35_host_get_pci_hole_start, 224 NULL, NULL, NULL); 225 226 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 227 q35_host_get_pci_hole_end, 228 NULL, NULL, NULL); 229 230 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 231 q35_host_get_pci_hole64_start, 232 NULL, NULL, NULL); 233 234 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 235 q35_host_get_pci_hole64_end, 236 NULL, NULL, NULL); 237 238 object_property_add_uint64_ptr(obj, PCIE_HOST_MCFG_SIZE, 239 &pehb->size, OBJ_PROP_FLAG_READ); 240 241 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 242 (Object **) &s->mch.ram_memory, 243 qdev_prop_allow_set_link_before_realize, 0); 244 245 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 246 (Object **) &s->mch.pci_address_space, 247 qdev_prop_allow_set_link_before_realize, 0); 248 249 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 250 (Object **) &s->mch.system_memory, 251 qdev_prop_allow_set_link_before_realize, 0); 252 253 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 254 (Object **) &s->mch.address_space_io, 255 qdev_prop_allow_set_link_before_realize, 0); 256 } 257 258 static const TypeInfo q35_host_info = { 259 .name = TYPE_Q35_HOST_DEVICE, 260 .parent = TYPE_PCIE_HOST_BRIDGE, 261 .instance_size = sizeof(Q35PCIHost), 262 .instance_init = q35_host_initfn, 263 .class_init = q35_host_class_init, 264 }; 265 266 /**************************************************************************** 267 * MCH D0:F0 268 */ 269 270 static uint64_t blackhole_read(void *ptr, hwaddr reg, unsigned size) 271 { 272 return 0xffffffff; 273 } 274 275 static void blackhole_write(void *opaque, hwaddr addr, uint64_t val, 276 unsigned width) 277 { 278 /* nothing */ 279 } 280 281 static const MemoryRegionOps blackhole_ops = { 282 .read = blackhole_read, 283 .write = blackhole_write, 284 .endianness = DEVICE_NATIVE_ENDIAN, 285 .valid.min_access_size = 1, 286 .valid.max_access_size = 4, 287 .impl.min_access_size = 4, 288 .impl.max_access_size = 4, 289 .endianness = DEVICE_LITTLE_ENDIAN, 290 }; 291 292 /* PCIe MMCFG */ 293 static void mch_update_pciexbar(MCHPCIState *mch) 294 { 295 PCIDevice *pci_dev = PCI_DEVICE(mch); 296 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 297 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 298 299 uint64_t pciexbar; 300 int enable; 301 uint64_t addr; 302 uint64_t addr_mask; 303 uint32_t length; 304 305 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 306 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 307 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 308 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 309 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 310 length = 256 * 1024 * 1024; 311 break; 312 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 313 length = 128 * 1024 * 1024; 314 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 315 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 316 break; 317 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 318 length = 64 * 1024 * 1024; 319 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 320 break; 321 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 322 default: 323 abort(); 324 } 325 addr = pciexbar & addr_mask; 326 pcie_host_mmcfg_update(pehb, enable, addr, length); 327 } 328 329 /* PAM */ 330 static void mch_update_pam(MCHPCIState *mch) 331 { 332 PCIDevice *pd = PCI_DEVICE(mch); 333 int i; 334 335 memory_region_transaction_begin(); 336 for (i = 0; i < 13; i++) { 337 pam_update(&mch->pam_regions[i], i, 338 pd->config[MCH_HOST_BRIDGE_PAM0 + DIV_ROUND_UP(i, 2)]); 339 } 340 memory_region_transaction_commit(); 341 } 342 343 /* SMRAM */ 344 static void mch_update_smram(MCHPCIState *mch) 345 { 346 PCIDevice *pd = PCI_DEVICE(mch); 347 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 348 uint32_t tseg_size; 349 350 /* implement SMRAM.D_LCK */ 351 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 352 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 353 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 354 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 355 } 356 357 memory_region_transaction_begin(); 358 359 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 360 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 361 memory_region_set_enabled(&mch->smram_region, h_smrame); 362 /* Show high SMRAM if H_SMRAME = 1 */ 363 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 364 } else { 365 /* Hide high SMRAM and low SMRAM */ 366 memory_region_set_enabled(&mch->smram_region, true); 367 memory_region_set_enabled(&mch->open_high_smram, false); 368 } 369 370 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 371 memory_region_set_enabled(&mch->low_smram, !h_smrame); 372 memory_region_set_enabled(&mch->high_smram, h_smrame); 373 } else { 374 memory_region_set_enabled(&mch->low_smram, false); 375 memory_region_set_enabled(&mch->high_smram, false); 376 } 377 378 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 379 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 380 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 381 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 382 tseg_size = 1024 * 1024; 383 break; 384 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 385 tseg_size = 1024 * 1024 * 2; 386 break; 387 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 388 tseg_size = 1024 * 1024 * 8; 389 break; 390 default: 391 tseg_size = 1024 * 1024 * (uint32_t)mch->ext_tseg_mbytes; 392 break; 393 } 394 } else { 395 tseg_size = 0; 396 } 397 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 398 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 399 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 400 memory_region_add_subregion_overlap(mch->system_memory, 401 mch->below_4g_mem_size - tseg_size, 402 &mch->tseg_blackhole, 1); 403 404 memory_region_set_enabled(&mch->tseg_window, tseg_size); 405 memory_region_set_size(&mch->tseg_window, tseg_size); 406 memory_region_set_address(&mch->tseg_window, 407 mch->below_4g_mem_size - tseg_size); 408 memory_region_set_alias_offset(&mch->tseg_window, 409 mch->below_4g_mem_size - tseg_size); 410 411 memory_region_transaction_commit(); 412 } 413 414 static void mch_update_ext_tseg_mbytes(MCHPCIState *mch) 415 { 416 PCIDevice *pd = PCI_DEVICE(mch); 417 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES; 418 419 if (mch->ext_tseg_mbytes > 0 && 420 pci_get_word(reg) == MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY) { 421 pci_set_word(reg, mch->ext_tseg_mbytes); 422 } 423 } 424 425 static void mch_update_smbase_smram(MCHPCIState *mch) 426 { 427 PCIDevice *pd = PCI_DEVICE(mch); 428 uint8_t *reg = pd->config + MCH_HOST_BRIDGE_F_SMBASE; 429 bool lck; 430 431 if (!mch->has_smram_at_smbase) { 432 return; 433 } 434 435 if (*reg == MCH_HOST_BRIDGE_F_SMBASE_QUERY) { 436 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 437 MCH_HOST_BRIDGE_F_SMBASE_LCK; 438 *reg = MCH_HOST_BRIDGE_F_SMBASE_IN_RAM; 439 return; 440 } 441 442 /* 443 * default/reset state, discard written value 444 * which will disable SMRAM balackhole at SMBASE 445 */ 446 if (pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] == 0xff) { 447 *reg = 0x00; 448 } 449 450 memory_region_transaction_begin(); 451 if (*reg & MCH_HOST_BRIDGE_F_SMBASE_LCK) { 452 /* disable all writes */ 453 pd->wmask[MCH_HOST_BRIDGE_F_SMBASE] &= 454 ~MCH_HOST_BRIDGE_F_SMBASE_LCK; 455 *reg = MCH_HOST_BRIDGE_F_SMBASE_LCK; 456 lck = true; 457 } else { 458 lck = false; 459 } 460 memory_region_set_enabled(&mch->smbase_blackhole, lck); 461 memory_region_set_enabled(&mch->smbase_window, lck); 462 memory_region_transaction_commit(); 463 } 464 465 static void mch_write_config(PCIDevice *d, 466 uint32_t address, uint32_t val, int len) 467 { 468 MCHPCIState *mch = MCH_PCI_DEVICE(d); 469 470 pci_default_write_config(d, address, val, len); 471 472 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 473 MCH_HOST_BRIDGE_PAM_SIZE)) { 474 mch_update_pam(mch); 475 } 476 477 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 478 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 479 mch_update_pciexbar(mch); 480 } 481 482 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 483 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 484 mch_update_smram(mch); 485 } 486 487 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 488 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_SIZE)) { 489 mch_update_ext_tseg_mbytes(mch); 490 } 491 492 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_F_SMBASE, 1)) { 493 mch_update_smbase_smram(mch); 494 } 495 } 496 497 static void mch_update(MCHPCIState *mch) 498 { 499 mch_update_pciexbar(mch); 500 mch_update_pam(mch); 501 mch_update_smram(mch); 502 mch_update_ext_tseg_mbytes(mch); 503 mch_update_smbase_smram(mch); 504 505 /* 506 * pci hole goes from end-of-low-ram to io-apic. 507 * mmconfig will be excluded by the dsdt builder. 508 */ 509 range_set_bounds(&mch->pci_hole, 510 mch->below_4g_mem_size, 511 IO_APIC_DEFAULT_ADDRESS - 1); 512 } 513 514 static int mch_post_load(void *opaque, int version_id) 515 { 516 MCHPCIState *mch = opaque; 517 mch_update(mch); 518 return 0; 519 } 520 521 static const VMStateDescription vmstate_mch = { 522 .name = "mch", 523 .version_id = 1, 524 .minimum_version_id = 1, 525 .post_load = mch_post_load, 526 .fields = (VMStateField[]) { 527 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 528 /* Used to be smm_enabled, which was basically always zero because 529 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 530 */ 531 VMSTATE_UNUSED(1), 532 VMSTATE_END_OF_LIST() 533 } 534 }; 535 536 static void mch_reset(DeviceState *qdev) 537 { 538 PCIDevice *d = PCI_DEVICE(qdev); 539 MCHPCIState *mch = MCH_PCI_DEVICE(d); 540 541 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 542 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 543 544 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 545 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 546 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 547 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 548 549 if (mch->ext_tseg_mbytes > 0) { 550 pci_set_word(d->config + MCH_HOST_BRIDGE_EXT_TSEG_MBYTES, 551 MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_QUERY); 552 } 553 554 d->config[MCH_HOST_BRIDGE_F_SMBASE] = 0; 555 d->wmask[MCH_HOST_BRIDGE_F_SMBASE] = 0xff; 556 557 mch_update(mch); 558 } 559 560 static void mch_realize(PCIDevice *d, Error **errp) 561 { 562 int i; 563 MCHPCIState *mch = MCH_PCI_DEVICE(d); 564 565 if (mch->ext_tseg_mbytes > MCH_HOST_BRIDGE_EXT_TSEG_MBYTES_MAX) { 566 error_setg(errp, "invalid extended-tseg-mbytes value: %" PRIu16, 567 mch->ext_tseg_mbytes); 568 return; 569 } 570 571 /* setup pci memory mapping */ 572 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 573 mch->pci_address_space); 574 575 /* if *disabled* show SMRAM to all CPUs */ 576 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 577 mch->pci_address_space, MCH_HOST_BRIDGE_SMRAM_C_BASE, 578 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 579 memory_region_add_subregion_overlap(mch->system_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 580 &mch->smram_region, 1); 581 memory_region_set_enabled(&mch->smram_region, true); 582 583 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 584 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 585 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 586 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 587 &mch->open_high_smram, 1); 588 memory_region_set_enabled(&mch->open_high_smram, false); 589 590 /* smram, as seen by SMM CPUs */ 591 memory_region_init(&mch->smram, OBJECT(mch), "smram", 4 * GiB); 592 memory_region_set_enabled(&mch->smram, true); 593 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 594 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 595 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 596 memory_region_set_enabled(&mch->low_smram, true); 597 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMRAM_C_BASE, 598 &mch->low_smram); 599 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 600 mch->ram_memory, MCH_HOST_BRIDGE_SMRAM_C_BASE, 601 MCH_HOST_BRIDGE_SMRAM_C_SIZE); 602 memory_region_set_enabled(&mch->high_smram, true); 603 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 604 605 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 606 &blackhole_ops, NULL, 607 "tseg-blackhole", 0); 608 memory_region_set_enabled(&mch->tseg_blackhole, false); 609 memory_region_add_subregion_overlap(mch->system_memory, 610 mch->below_4g_mem_size, 611 &mch->tseg_blackhole, 1); 612 613 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 614 mch->ram_memory, mch->below_4g_mem_size, 0); 615 memory_region_set_enabled(&mch->tseg_window, false); 616 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 617 &mch->tseg_window); 618 619 /* 620 * This is not what hardware does, so it's QEMU specific hack. 621 * See commit message for details. 622 */ 623 memory_region_init_io(&mch->smbase_blackhole, OBJECT(mch), &blackhole_ops, 624 NULL, "smbase-blackhole", 625 MCH_HOST_BRIDGE_SMBASE_SIZE); 626 memory_region_set_enabled(&mch->smbase_blackhole, false); 627 memory_region_add_subregion_overlap(mch->system_memory, 628 MCH_HOST_BRIDGE_SMBASE_ADDR, 629 &mch->smbase_blackhole, 1); 630 631 memory_region_init_alias(&mch->smbase_window, OBJECT(mch), 632 "smbase-window", mch->ram_memory, 633 MCH_HOST_BRIDGE_SMBASE_ADDR, 634 MCH_HOST_BRIDGE_SMBASE_SIZE); 635 memory_region_set_enabled(&mch->smbase_window, false); 636 memory_region_add_subregion(&mch->smram, MCH_HOST_BRIDGE_SMBASE_ADDR, 637 &mch->smbase_window); 638 639 object_property_add_const_link(qdev_get_machine(), "smram", 640 OBJECT(&mch->smram)); 641 642 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 643 mch->pci_address_space, &mch->pam_regions[0], 644 PAM_BIOS_BASE, PAM_BIOS_SIZE); 645 for (i = 0; i < 12; ++i) { 646 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 647 mch->pci_address_space, &mch->pam_regions[i+1], 648 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 649 } 650 } 651 652 uint64_t mch_mcfg_base(void) 653 { 654 bool ambiguous; 655 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 656 if (!o) { 657 return 0; 658 } 659 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 660 } 661 662 static Property mch_props[] = { 663 DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 664 16), 665 DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), 666 DEFINE_PROP_END_OF_LIST(), 667 }; 668 669 static void mch_class_init(ObjectClass *klass, void *data) 670 { 671 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 672 DeviceClass *dc = DEVICE_CLASS(klass); 673 674 k->realize = mch_realize; 675 k->config_write = mch_write_config; 676 dc->reset = mch_reset; 677 device_class_set_props(dc, mch_props); 678 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 679 dc->desc = "Host bridge"; 680 dc->vmsd = &vmstate_mch; 681 k->vendor_id = PCI_VENDOR_ID_INTEL; 682 /* 683 * The 'q35' machine type implements an Intel Series 3 chipset, 684 * of which there are several variants. The key difference between 685 * the 82P35 MCH ('p35') and 82Q35 GMCH ('q35') variants is that 686 * the latter has an integrated graphics adapter. QEMU does not 687 * implement integrated graphics, so uses the PCI ID for the 82P35 688 * chipset. 689 */ 690 k->device_id = PCI_DEVICE_ID_INTEL_P35_MCH; 691 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 692 k->class_id = PCI_CLASS_BRIDGE_HOST; 693 /* 694 * PCI-facing part of the host bridge, not usable without the 695 * host-facing part, which can't be device_add'ed, yet. 696 */ 697 dc->user_creatable = false; 698 } 699 700 static const TypeInfo mch_info = { 701 .name = TYPE_MCH_PCI_DEVICE, 702 .parent = TYPE_PCI_DEVICE, 703 .instance_size = sizeof(MCHPCIState), 704 .class_init = mch_class_init, 705 .interfaces = (InterfaceInfo[]) { 706 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 707 { }, 708 }, 709 }; 710 711 static void q35_register(void) 712 { 713 type_register_static(&mch_info); 714 type_register_static(&q35_host_info); 715 } 716 717 type_init(q35_register); 718