1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix_pci.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "hw/hw.h" 31 #include "hw/pci-host/q35.h" 32 33 /**************************************************************************** 34 * Q35 host 35 */ 36 37 static void q35_host_realize(DeviceState *dev, Error **errp) 38 { 39 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 40 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 41 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 42 43 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 44 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 45 46 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 47 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 48 49 if (pcie_host_init(PCIE_HOST_BRIDGE(s)) < 0) { 50 error_setg(errp, "failed to initialize pcie host"); 51 return; 52 } 53 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 54 s->mch.pci_address_space, s->mch.address_space_io, 55 0, TYPE_PCIE_BUS); 56 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 57 qdev_init_nofail(DEVICE(&s->mch)); 58 } 59 60 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 61 PCIBus *rootbus) 62 { 63 /* For backwards compat with old device paths */ 64 return "0000"; 65 } 66 67 static Property mch_props[] = { 68 DEFINE_PROP_UINT64("MCFG", Q35PCIHost, parent_obj.base_addr, 69 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 70 DEFINE_PROP_END_OF_LIST(), 71 }; 72 73 static void q35_host_class_init(ObjectClass *klass, void *data) 74 { 75 DeviceClass *dc = DEVICE_CLASS(klass); 76 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 77 78 hc->root_bus_path = q35_host_root_bus_path; 79 dc->realize = q35_host_realize; 80 dc->props = mch_props; 81 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 82 dc->fw_name = "pci"; 83 } 84 85 static void q35_host_initfn(Object *obj) 86 { 87 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 88 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 89 90 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 91 "pci-conf-idx", 4); 92 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 93 "pci-conf-data", 4); 94 95 object_initialize(&s->mch, TYPE_MCH_PCI_DEVICE); 96 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 97 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 98 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 99 } 100 101 static const TypeInfo q35_host_info = { 102 .name = TYPE_Q35_HOST_DEVICE, 103 .parent = TYPE_PCIE_HOST_BRIDGE, 104 .instance_size = sizeof(Q35PCIHost), 105 .instance_init = q35_host_initfn, 106 .class_init = q35_host_class_init, 107 }; 108 109 /**************************************************************************** 110 * MCH D0:F0 111 */ 112 113 /* PCIe MMCFG */ 114 static void mch_update_pciexbar(MCHPCIState *mch) 115 { 116 PCIDevice *pci_dev = PCI_DEVICE(mch); 117 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 118 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 119 120 uint64_t pciexbar; 121 int enable; 122 uint64_t addr; 123 uint64_t addr_mask; 124 uint32_t length; 125 126 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 127 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 128 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 129 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 130 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 131 length = 256 * 1024 * 1024; 132 break; 133 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 134 length = 128 * 1024 * 1024; 135 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 136 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 137 break; 138 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 139 length = 64 * 1024 * 1024; 140 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 141 break; 142 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 143 default: 144 enable = 0; 145 length = 0; 146 abort(); 147 break; 148 } 149 addr = pciexbar & addr_mask; 150 pcie_host_mmcfg_update(pehb, enable, addr, length); 151 } 152 153 /* PAM */ 154 static void mch_update_pam(MCHPCIState *mch) 155 { 156 PCIDevice *pd = PCI_DEVICE(mch); 157 int i; 158 159 memory_region_transaction_begin(); 160 for (i = 0; i < 13; i++) { 161 pam_update(&mch->pam_regions[i], i, 162 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 163 } 164 memory_region_transaction_commit(); 165 } 166 167 /* SMRAM */ 168 static void mch_update_smram(MCHPCIState *mch) 169 { 170 PCIDevice *pd = PCI_DEVICE(mch); 171 172 memory_region_transaction_begin(); 173 smram_update(&mch->smram_region, pd->config[MCH_HOST_BRDIGE_SMRAM], 174 mch->smm_enabled); 175 memory_region_transaction_commit(); 176 } 177 178 static void mch_set_smm(int smm, void *arg) 179 { 180 MCHPCIState *mch = arg; 181 PCIDevice *pd = PCI_DEVICE(mch); 182 183 memory_region_transaction_begin(); 184 smram_set_smm(&mch->smm_enabled, smm, pd->config[MCH_HOST_BRDIGE_SMRAM], 185 &mch->smram_region); 186 memory_region_transaction_commit(); 187 } 188 189 static void mch_write_config(PCIDevice *d, 190 uint32_t address, uint32_t val, int len) 191 { 192 MCHPCIState *mch = MCH_PCI_DEVICE(d); 193 194 /* XXX: implement SMRAM.D_LOCK */ 195 pci_default_write_config(d, address, val, len); 196 197 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 198 MCH_HOST_BRIDGE_PAM_SIZE)) { 199 mch_update_pam(mch); 200 } 201 202 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 203 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 204 mch_update_pciexbar(mch); 205 } 206 207 if (ranges_overlap(address, len, MCH_HOST_BRDIGE_SMRAM, 208 MCH_HOST_BRDIGE_SMRAM_SIZE)) { 209 mch_update_smram(mch); 210 } 211 } 212 213 static void mch_update(MCHPCIState *mch) 214 { 215 mch_update_pciexbar(mch); 216 mch_update_pam(mch); 217 mch_update_smram(mch); 218 } 219 220 static int mch_post_load(void *opaque, int version_id) 221 { 222 MCHPCIState *mch = opaque; 223 mch_update(mch); 224 return 0; 225 } 226 227 static const VMStateDescription vmstate_mch = { 228 .name = "mch", 229 .version_id = 1, 230 .minimum_version_id = 1, 231 .minimum_version_id_old = 1, 232 .post_load = mch_post_load, 233 .fields = (VMStateField []) { 234 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 235 VMSTATE_UINT8(smm_enabled, MCHPCIState), 236 VMSTATE_END_OF_LIST() 237 } 238 }; 239 240 static void mch_reset(DeviceState *qdev) 241 { 242 PCIDevice *d = PCI_DEVICE(qdev); 243 MCHPCIState *mch = MCH_PCI_DEVICE(d); 244 245 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 246 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 247 248 d->config[MCH_HOST_BRDIGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 249 250 mch_update(mch); 251 } 252 253 static int mch_init(PCIDevice *d) 254 { 255 int i; 256 hwaddr pci_hole64_size; 257 MCHPCIState *mch = MCH_PCI_DEVICE(d); 258 259 /* Leave enough space for the biggest MCFG BAR */ 260 /* TODO: this matches current bios behaviour, but 261 * it's not a power of two, which means an MTRR 262 * can't cover it exactly. 263 */ 264 mch->guest_info->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 265 MCH_HOST_BRIDGE_PCIEXBAR_MAX; 266 267 /* setup pci memory regions */ 268 memory_region_init_alias(&mch->pci_hole, OBJECT(mch), "pci-hole", 269 mch->pci_address_space, 270 mch->below_4g_mem_size, 271 0x100000000ULL - mch->below_4g_mem_size); 272 memory_region_add_subregion(mch->system_memory, mch->below_4g_mem_size, 273 &mch->pci_hole); 274 pci_hole64_size = (sizeof(hwaddr) == 4 ? 0 : 275 ((uint64_t)1 << 62)); 276 memory_region_init_alias(&mch->pci_hole_64bit, OBJECT(mch), "pci-hole64", 277 mch->pci_address_space, 278 0x100000000ULL + mch->above_4g_mem_size, 279 pci_hole64_size); 280 if (pci_hole64_size) { 281 memory_region_add_subregion(mch->system_memory, 282 0x100000000ULL + mch->above_4g_mem_size, 283 &mch->pci_hole_64bit); 284 } 285 /* smram */ 286 cpu_smm_register(&mch_set_smm, mch); 287 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 288 mch->pci_address_space, 0xa0000, 0x20000); 289 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 290 &mch->smram_region, 1); 291 memory_region_set_enabled(&mch->smram_region, false); 292 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 293 &mch->pam_regions[0], PAM_BIOS_BASE, PAM_BIOS_SIZE); 294 for (i = 0; i < 12; ++i) { 295 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, mch->pci_address_space, 296 &mch->pam_regions[i+1], PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, 297 PAM_EXPAN_SIZE); 298 } 299 return 0; 300 } 301 302 static void mch_class_init(ObjectClass *klass, void *data) 303 { 304 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 305 DeviceClass *dc = DEVICE_CLASS(klass); 306 307 k->init = mch_init; 308 k->config_write = mch_write_config; 309 dc->reset = mch_reset; 310 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 311 dc->desc = "Host bridge"; 312 dc->vmsd = &vmstate_mch; 313 k->vendor_id = PCI_VENDOR_ID_INTEL; 314 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 315 k->revision = MCH_HOST_BRIDGE_REVISION_DEFUALT; 316 k->class_id = PCI_CLASS_BRIDGE_HOST; 317 } 318 319 static const TypeInfo mch_info = { 320 .name = TYPE_MCH_PCI_DEVICE, 321 .parent = TYPE_PCI_DEVICE, 322 .instance_size = sizeof(MCHPCIState), 323 .class_init = mch_class_init, 324 }; 325 326 static void q35_register(void) 327 { 328 type_register_static(&mch_info); 329 type_register_static(&q35_host_info); 330 } 331 332 type_init(q35_register); 333