1 /* 2 * QEMU MCH/ICH9 PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2009, 2010, 2011 6 * Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * Copyright (C) 2012 Jason Baron <jbaron@redhat.com> 9 * 10 * This is based on piix.c, but heavily modified. 11 * 12 * Permission is hereby granted, free of charge, to any person obtaining a copy 13 * of this software and associated documentation files (the "Software"), to deal 14 * in the Software without restriction, including without limitation the rights 15 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 16 * copies of the Software, and to permit persons to whom the Software is 17 * furnished to do so, subject to the following conditions: 18 * 19 * The above copyright notice and this permission notice shall be included in 20 * all copies or substantial portions of the Software. 21 * 22 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 23 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 24 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 25 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 26 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 27 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 28 * THE SOFTWARE. 29 */ 30 #include "qemu/osdep.h" 31 #include "hw/hw.h" 32 #include "hw/pci-host/q35.h" 33 #include "qapi/error.h" 34 #include "qapi/visitor.h" 35 36 /**************************************************************************** 37 * Q35 host 38 */ 39 40 static void q35_host_realize(DeviceState *dev, Error **errp) 41 { 42 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 43 Q35PCIHost *s = Q35_HOST_DEVICE(dev); 44 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 45 46 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, &pci->conf_mem); 47 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_ADDR, 4); 48 49 sysbus_add_io(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, &pci->data_mem); 50 sysbus_init_ioports(sbd, MCH_HOST_BRIDGE_CONFIG_DATA, 4); 51 52 pci->bus = pci_bus_new(DEVICE(s), "pcie.0", 53 s->mch.pci_address_space, s->mch.address_space_io, 54 0, TYPE_PCIE_BUS); 55 PC_MACHINE(qdev_get_machine())->bus = pci->bus; 56 qdev_set_parent_bus(DEVICE(&s->mch), BUS(pci->bus)); 57 qdev_init_nofail(DEVICE(&s->mch)); 58 } 59 60 static const char *q35_host_root_bus_path(PCIHostState *host_bridge, 61 PCIBus *rootbus) 62 { 63 Q35PCIHost *s = Q35_HOST_DEVICE(host_bridge); 64 65 /* For backwards compat with old device paths */ 66 if (s->mch.short_root_bus) { 67 return "0000"; 68 } 69 return "0000:00"; 70 } 71 72 static void q35_host_get_pci_hole_start(Object *obj, Visitor *v, 73 const char *name, void *opaque, 74 Error **errp) 75 { 76 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 77 uint32_t value = s->mch.pci_info.w32.begin; 78 79 visit_type_uint32(v, name, &value, errp); 80 } 81 82 static void q35_host_get_pci_hole_end(Object *obj, Visitor *v, 83 const char *name, void *opaque, 84 Error **errp) 85 { 86 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 87 uint32_t value = s->mch.pci_info.w32.end; 88 89 visit_type_uint32(v, name, &value, errp); 90 } 91 92 static void q35_host_get_pci_hole64_start(Object *obj, Visitor *v, 93 const char *name, void *opaque, 94 Error **errp) 95 { 96 PCIHostState *h = PCI_HOST_BRIDGE(obj); 97 Range w64; 98 99 pci_bus_get_w64_range(h->bus, &w64); 100 101 visit_type_uint64(v, name, &w64.begin, errp); 102 } 103 104 static void q35_host_get_pci_hole64_end(Object *obj, Visitor *v, 105 const char *name, void *opaque, 106 Error **errp) 107 { 108 PCIHostState *h = PCI_HOST_BRIDGE(obj); 109 Range w64; 110 111 pci_bus_get_w64_range(h->bus, &w64); 112 113 visit_type_uint64(v, name, &w64.end, errp); 114 } 115 116 static void q35_host_get_mmcfg_size(Object *obj, Visitor *v, const char *name, 117 void *opaque, Error **errp) 118 { 119 PCIExpressHost *e = PCIE_HOST_BRIDGE(obj); 120 uint32_t value = e->size; 121 122 visit_type_uint32(v, name, &value, errp); 123 } 124 125 static Property mch_props[] = { 126 DEFINE_PROP_UINT64(PCIE_HOST_MCFG_BASE, Q35PCIHost, parent_obj.base_addr, 127 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT), 128 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, Q35PCIHost, 129 mch.pci_hole64_size, DEFAULT_PCI_HOLE64_SIZE), 130 DEFINE_PROP_UINT32("short_root_bus", Q35PCIHost, mch.short_root_bus, 0), 131 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, Q35PCIHost, 132 mch.below_4g_mem_size, 0), 133 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, Q35PCIHost, 134 mch.above_4g_mem_size, 0), 135 DEFINE_PROP_END_OF_LIST(), 136 }; 137 138 static void q35_host_class_init(ObjectClass *klass, void *data) 139 { 140 DeviceClass *dc = DEVICE_CLASS(klass); 141 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 142 143 hc->root_bus_path = q35_host_root_bus_path; 144 dc->realize = q35_host_realize; 145 dc->props = mch_props; 146 /* Reason: needs to be wired up by pc_q35_init */ 147 dc->cannot_instantiate_with_device_add_yet = true; 148 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 149 dc->fw_name = "pci"; 150 } 151 152 static void q35_host_initfn(Object *obj) 153 { 154 Q35PCIHost *s = Q35_HOST_DEVICE(obj); 155 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 156 157 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 158 "pci-conf-idx", 4); 159 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 160 "pci-conf-data", 4); 161 162 object_initialize(&s->mch, sizeof(s->mch), TYPE_MCH_PCI_DEVICE); 163 object_property_add_child(OBJECT(s), "mch", OBJECT(&s->mch), NULL); 164 qdev_prop_set_uint32(DEVICE(&s->mch), "addr", PCI_DEVFN(0, 0)); 165 qdev_prop_set_bit(DEVICE(&s->mch), "multifunction", false); 166 167 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_START, "int", 168 q35_host_get_pci_hole_start, 169 NULL, NULL, NULL, NULL); 170 171 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE_END, "int", 172 q35_host_get_pci_hole_end, 173 NULL, NULL, NULL, NULL); 174 175 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_START, "int", 176 q35_host_get_pci_hole64_start, 177 NULL, NULL, NULL, NULL); 178 179 object_property_add(obj, PCI_HOST_PROP_PCI_HOLE64_END, "int", 180 q35_host_get_pci_hole64_end, 181 NULL, NULL, NULL, NULL); 182 183 object_property_add(obj, PCIE_HOST_MCFG_SIZE, "int", 184 q35_host_get_mmcfg_size, 185 NULL, NULL, NULL, NULL); 186 187 object_property_add_link(obj, MCH_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 188 (Object **) &s->mch.ram_memory, 189 qdev_prop_allow_set_link_before_realize, 0, NULL); 190 191 object_property_add_link(obj, MCH_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 192 (Object **) &s->mch.pci_address_space, 193 qdev_prop_allow_set_link_before_realize, 0, NULL); 194 195 object_property_add_link(obj, MCH_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 196 (Object **) &s->mch.system_memory, 197 qdev_prop_allow_set_link_before_realize, 0, NULL); 198 199 object_property_add_link(obj, MCH_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 200 (Object **) &s->mch.address_space_io, 201 qdev_prop_allow_set_link_before_realize, 0, NULL); 202 203 /* Leave enough space for the biggest MCFG BAR */ 204 /* TODO: this matches current bios behaviour, but 205 * it's not a power of two, which means an MTRR 206 * can't cover it exactly. 207 */ 208 s->mch.pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT + 209 MCH_HOST_BRIDGE_PCIEXBAR_MAX; 210 s->mch.pci_info.w32.end = IO_APIC_DEFAULT_ADDRESS; 211 } 212 213 static const TypeInfo q35_host_info = { 214 .name = TYPE_Q35_HOST_DEVICE, 215 .parent = TYPE_PCIE_HOST_BRIDGE, 216 .instance_size = sizeof(Q35PCIHost), 217 .instance_init = q35_host_initfn, 218 .class_init = q35_host_class_init, 219 }; 220 221 /**************************************************************************** 222 * MCH D0:F0 223 */ 224 225 static uint64_t tseg_blackhole_read(void *ptr, hwaddr reg, unsigned size) 226 { 227 return 0xffffffff; 228 } 229 230 static void tseg_blackhole_write(void *opaque, hwaddr addr, uint64_t val, 231 unsigned width) 232 { 233 /* nothing */ 234 } 235 236 static const MemoryRegionOps tseg_blackhole_ops = { 237 .read = tseg_blackhole_read, 238 .write = tseg_blackhole_write, 239 .endianness = DEVICE_NATIVE_ENDIAN, 240 .valid.min_access_size = 1, 241 .valid.max_access_size = 4, 242 .impl.min_access_size = 4, 243 .impl.max_access_size = 4, 244 .endianness = DEVICE_LITTLE_ENDIAN, 245 }; 246 247 /* PCIe MMCFG */ 248 static void mch_update_pciexbar(MCHPCIState *mch) 249 { 250 PCIDevice *pci_dev = PCI_DEVICE(mch); 251 BusState *bus = qdev_get_parent_bus(DEVICE(mch)); 252 PCIExpressHost *pehb = PCIE_HOST_BRIDGE(bus->parent); 253 254 uint64_t pciexbar; 255 int enable; 256 uint64_t addr; 257 uint64_t addr_mask; 258 uint32_t length; 259 260 pciexbar = pci_get_quad(pci_dev->config + MCH_HOST_BRIDGE_PCIEXBAR); 261 enable = pciexbar & MCH_HOST_BRIDGE_PCIEXBAREN; 262 addr_mask = MCH_HOST_BRIDGE_PCIEXBAR_ADMSK; 263 switch (pciexbar & MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_MASK) { 264 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_256M: 265 length = 256 * 1024 * 1024; 266 break; 267 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_128M: 268 length = 128 * 1024 * 1024; 269 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_128ADMSK | 270 MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 271 break; 272 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_64M: 273 length = 64 * 1024 * 1024; 274 addr_mask |= MCH_HOST_BRIDGE_PCIEXBAR_64ADMSK; 275 break; 276 case MCH_HOST_BRIDGE_PCIEXBAR_LENGTH_RVD: 277 default: 278 enable = 0; 279 length = 0; 280 abort(); 281 break; 282 } 283 addr = pciexbar & addr_mask; 284 pcie_host_mmcfg_update(pehb, enable, addr, length); 285 /* Leave enough space for the MCFG BAR */ 286 /* 287 * TODO: this matches current bios behaviour, but it's not a power of two, 288 * which means an MTRR can't cover it exactly. 289 */ 290 if (enable) { 291 mch->pci_info.w32.begin = addr + length; 292 } else { 293 mch->pci_info.w32.begin = MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 294 } 295 } 296 297 /* PAM */ 298 static void mch_update_pam(MCHPCIState *mch) 299 { 300 PCIDevice *pd = PCI_DEVICE(mch); 301 int i; 302 303 memory_region_transaction_begin(); 304 for (i = 0; i < 13; i++) { 305 pam_update(&mch->pam_regions[i], i, 306 pd->config[MCH_HOST_BRIDGE_PAM0 + ((i + 1) / 2)]); 307 } 308 memory_region_transaction_commit(); 309 } 310 311 /* SMRAM */ 312 static void mch_update_smram(MCHPCIState *mch) 313 { 314 PCIDevice *pd = PCI_DEVICE(mch); 315 bool h_smrame = (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_H_SMRAME); 316 uint32_t tseg_size; 317 318 /* implement SMRAM.D_LCK */ 319 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & MCH_HOST_BRIDGE_SMRAM_D_LCK) { 320 pd->config[MCH_HOST_BRIDGE_SMRAM] &= ~MCH_HOST_BRIDGE_SMRAM_D_OPEN; 321 pd->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK_LCK; 322 pd->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK_LCK; 323 } 324 325 memory_region_transaction_begin(); 326 327 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_D_OPEN) { 328 /* Hide (!) low SMRAM if H_SMRAME = 1 */ 329 memory_region_set_enabled(&mch->smram_region, h_smrame); 330 /* Show high SMRAM if H_SMRAME = 1 */ 331 memory_region_set_enabled(&mch->open_high_smram, h_smrame); 332 } else { 333 /* Hide high SMRAM and low SMRAM */ 334 memory_region_set_enabled(&mch->smram_region, true); 335 memory_region_set_enabled(&mch->open_high_smram, false); 336 } 337 338 if (pd->config[MCH_HOST_BRIDGE_SMRAM] & SMRAM_G_SMRAME) { 339 memory_region_set_enabled(&mch->low_smram, !h_smrame); 340 memory_region_set_enabled(&mch->high_smram, h_smrame); 341 } else { 342 memory_region_set_enabled(&mch->low_smram, false); 343 memory_region_set_enabled(&mch->high_smram, false); 344 } 345 346 if (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & MCH_HOST_BRIDGE_ESMRAMC_T_EN) { 347 switch (pd->config[MCH_HOST_BRIDGE_ESMRAMC] & 348 MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_MASK) { 349 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_1MB: 350 tseg_size = 1024 * 1024; 351 break; 352 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_2MB: 353 tseg_size = 1024 * 1024 * 2; 354 break; 355 case MCH_HOST_BRIDGE_ESMRAMC_TSEG_SZ_8MB: 356 tseg_size = 1024 * 1024 * 8; 357 break; 358 default: 359 tseg_size = 0; 360 break; 361 } 362 } else { 363 tseg_size = 0; 364 } 365 memory_region_del_subregion(mch->system_memory, &mch->tseg_blackhole); 366 memory_region_set_enabled(&mch->tseg_blackhole, tseg_size); 367 memory_region_set_size(&mch->tseg_blackhole, tseg_size); 368 memory_region_add_subregion_overlap(mch->system_memory, 369 mch->below_4g_mem_size - tseg_size, 370 &mch->tseg_blackhole, 1); 371 372 memory_region_set_enabled(&mch->tseg_window, tseg_size); 373 memory_region_set_size(&mch->tseg_window, tseg_size); 374 memory_region_set_address(&mch->tseg_window, 375 mch->below_4g_mem_size - tseg_size); 376 memory_region_set_alias_offset(&mch->tseg_window, 377 mch->below_4g_mem_size - tseg_size); 378 379 memory_region_transaction_commit(); 380 } 381 382 static void mch_write_config(PCIDevice *d, 383 uint32_t address, uint32_t val, int len) 384 { 385 MCHPCIState *mch = MCH_PCI_DEVICE(d); 386 387 pci_default_write_config(d, address, val, len); 388 389 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PAM0, 390 MCH_HOST_BRIDGE_PAM_SIZE)) { 391 mch_update_pam(mch); 392 } 393 394 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_PCIEXBAR, 395 MCH_HOST_BRIDGE_PCIEXBAR_SIZE)) { 396 mch_update_pciexbar(mch); 397 } 398 399 if (ranges_overlap(address, len, MCH_HOST_BRIDGE_SMRAM, 400 MCH_HOST_BRIDGE_SMRAM_SIZE)) { 401 mch_update_smram(mch); 402 } 403 } 404 405 static void mch_update(MCHPCIState *mch) 406 { 407 mch_update_pciexbar(mch); 408 mch_update_pam(mch); 409 mch_update_smram(mch); 410 } 411 412 static int mch_post_load(void *opaque, int version_id) 413 { 414 MCHPCIState *mch = opaque; 415 mch_update(mch); 416 return 0; 417 } 418 419 static const VMStateDescription vmstate_mch = { 420 .name = "mch", 421 .version_id = 1, 422 .minimum_version_id = 1, 423 .post_load = mch_post_load, 424 .fields = (VMStateField[]) { 425 VMSTATE_PCI_DEVICE(parent_obj, MCHPCIState), 426 /* Used to be smm_enabled, which was basically always zero because 427 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 428 */ 429 VMSTATE_UNUSED(1), 430 VMSTATE_END_OF_LIST() 431 } 432 }; 433 434 static void mch_reset(DeviceState *qdev) 435 { 436 PCIDevice *d = PCI_DEVICE(qdev); 437 MCHPCIState *mch = MCH_PCI_DEVICE(d); 438 439 pci_set_quad(d->config + MCH_HOST_BRIDGE_PCIEXBAR, 440 MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT); 441 442 d->config[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_DEFAULT; 443 d->config[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_DEFAULT; 444 d->wmask[MCH_HOST_BRIDGE_SMRAM] = MCH_HOST_BRIDGE_SMRAM_WMASK; 445 d->wmask[MCH_HOST_BRIDGE_ESMRAMC] = MCH_HOST_BRIDGE_ESMRAMC_WMASK; 446 447 mch_update(mch); 448 } 449 450 static void mch_realize(PCIDevice *d, Error **errp) 451 { 452 int i; 453 MCHPCIState *mch = MCH_PCI_DEVICE(d); 454 455 /* setup pci memory mapping */ 456 pc_pci_as_mapping_init(OBJECT(mch), mch->system_memory, 457 mch->pci_address_space); 458 459 /* if *disabled* show SMRAM to all CPUs */ 460 memory_region_init_alias(&mch->smram_region, OBJECT(mch), "smram-region", 461 mch->pci_address_space, 0xa0000, 0x20000); 462 memory_region_add_subregion_overlap(mch->system_memory, 0xa0000, 463 &mch->smram_region, 1); 464 memory_region_set_enabled(&mch->smram_region, true); 465 466 memory_region_init_alias(&mch->open_high_smram, OBJECT(mch), "smram-open-high", 467 mch->ram_memory, 0xa0000, 0x20000); 468 memory_region_add_subregion_overlap(mch->system_memory, 0xfeda0000, 469 &mch->open_high_smram, 1); 470 memory_region_set_enabled(&mch->open_high_smram, false); 471 472 /* smram, as seen by SMM CPUs */ 473 memory_region_init(&mch->smram, OBJECT(mch), "smram", 1ull << 32); 474 memory_region_set_enabled(&mch->smram, true); 475 memory_region_init_alias(&mch->low_smram, OBJECT(mch), "smram-low", 476 mch->ram_memory, 0xa0000, 0x20000); 477 memory_region_set_enabled(&mch->low_smram, true); 478 memory_region_add_subregion(&mch->smram, 0xa0000, &mch->low_smram); 479 memory_region_init_alias(&mch->high_smram, OBJECT(mch), "smram-high", 480 mch->ram_memory, 0xa0000, 0x20000); 481 memory_region_set_enabled(&mch->high_smram, true); 482 memory_region_add_subregion(&mch->smram, 0xfeda0000, &mch->high_smram); 483 484 memory_region_init_io(&mch->tseg_blackhole, OBJECT(mch), 485 &tseg_blackhole_ops, NULL, 486 "tseg-blackhole", 0); 487 memory_region_set_enabled(&mch->tseg_blackhole, false); 488 memory_region_add_subregion_overlap(mch->system_memory, 489 mch->below_4g_mem_size, 490 &mch->tseg_blackhole, 1); 491 492 memory_region_init_alias(&mch->tseg_window, OBJECT(mch), "tseg-window", 493 mch->ram_memory, mch->below_4g_mem_size, 0); 494 memory_region_set_enabled(&mch->tseg_window, false); 495 memory_region_add_subregion(&mch->smram, mch->below_4g_mem_size, 496 &mch->tseg_window); 497 object_property_add_const_link(qdev_get_machine(), "smram", 498 OBJECT(&mch->smram), &error_abort); 499 500 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 501 mch->pci_address_space, &mch->pam_regions[0], 502 PAM_BIOS_BASE, PAM_BIOS_SIZE); 503 for (i = 0; i < 12; ++i) { 504 init_pam(DEVICE(mch), mch->ram_memory, mch->system_memory, 505 mch->pci_address_space, &mch->pam_regions[i+1], 506 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 507 } 508 } 509 510 uint64_t mch_mcfg_base(void) 511 { 512 bool ambiguous; 513 Object *o = object_resolve_path_type("", TYPE_MCH_PCI_DEVICE, &ambiguous); 514 if (!o) { 515 return 0; 516 } 517 return MCH_HOST_BRIDGE_PCIEXBAR_DEFAULT; 518 } 519 520 static void mch_class_init(ObjectClass *klass, void *data) 521 { 522 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 523 DeviceClass *dc = DEVICE_CLASS(klass); 524 525 k->realize = mch_realize; 526 k->config_write = mch_write_config; 527 dc->reset = mch_reset; 528 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 529 dc->desc = "Host bridge"; 530 dc->vmsd = &vmstate_mch; 531 k->vendor_id = PCI_VENDOR_ID_INTEL; 532 k->device_id = PCI_DEVICE_ID_INTEL_Q35_MCH; 533 k->revision = MCH_HOST_BRIDGE_REVISION_DEFAULT; 534 k->class_id = PCI_CLASS_BRIDGE_HOST; 535 /* 536 * PCI-facing part of the host bridge, not usable without the 537 * host-facing part, which can't be device_add'ed, yet. 538 */ 539 dc->cannot_instantiate_with_device_add_yet = true; 540 } 541 542 static const TypeInfo mch_info = { 543 .name = TYPE_MCH_PCI_DEVICE, 544 .parent = TYPE_PCI_DEVICE, 545 .instance_size = sizeof(MCHPCIState), 546 .class_init = mch_class_init, 547 }; 548 549 static void q35_register(void) 550 { 551 type_register_static(&mch_info); 552 type_register_static(&q35_host_info); 553 } 554 555 type_init(q35_register); 556