1 /* 2 * QEMU PowerPC E500 embedded processors pci controller emulation 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc4xx_pci.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "qemu/osdep.h" 18 #include "hw/hw.h" 19 #include "hw/ppc/e500-ccsr.h" 20 #include "hw/pci/pci.h" 21 #include "hw/pci/pci_host.h" 22 #include "qemu/bswap.h" 23 #include "hw/pci-host/ppce500.h" 24 25 #ifdef DEBUG_PCI 26 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) 27 #else 28 #define pci_debug(fmt, ...) 29 #endif 30 31 #define PCIE500_CFGADDR 0x0 32 #define PCIE500_CFGDATA 0x4 33 #define PCIE500_REG_BASE 0xC00 34 #define PCIE500_ALL_SIZE 0x1000 35 #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) 36 37 #define PCIE500_PCI_IOLEN 0x10000ULL 38 39 #define PPCE500_PCI_CONFIG_ADDR 0x0 40 #define PPCE500_PCI_CONFIG_DATA 0x4 41 #define PPCE500_PCI_INTACK 0x8 42 43 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) 44 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) 45 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) 46 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) 47 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) 48 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) 49 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) 50 51 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) 52 53 #define PCI_POTAR 0x0 54 #define PCI_POTEAR 0x4 55 #define PCI_POWBAR 0x8 56 #define PCI_POWAR 0x10 57 58 #define PCI_PITAR 0x0 59 #define PCI_PIWBAR 0x8 60 #define PCI_PIWBEAR 0xC 61 #define PCI_PIWAR 0x10 62 63 #define PPCE500_PCI_NR_POBS 5 64 #define PPCE500_PCI_NR_PIBS 3 65 66 #define PIWAR_EN 0x80000000 /* Enable */ 67 #define PIWAR_PF 0x20000000 /* prefetch */ 68 #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 69 #define PIWAR_READ_SNOOP 0x00050000 70 #define PIWAR_WRITE_SNOOP 0x00005000 71 #define PIWAR_SZ_MASK 0x0000003f 72 73 struct pci_outbound { 74 uint32_t potar; 75 uint32_t potear; 76 uint32_t powbar; 77 uint32_t powar; 78 MemoryRegion mem; 79 }; 80 81 struct pci_inbound { 82 uint32_t pitar; 83 uint32_t piwbar; 84 uint32_t piwbear; 85 uint32_t piwar; 86 MemoryRegion mem; 87 }; 88 89 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" 90 91 #define PPC_E500_PCI_HOST_BRIDGE(obj) \ 92 OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE) 93 94 struct PPCE500PCIState { 95 PCIHostState parent_obj; 96 97 struct pci_outbound pob[PPCE500_PCI_NR_POBS]; 98 struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; 99 uint32_t gasket_time; 100 qemu_irq irq[PCI_NUM_PINS]; 101 uint32_t irq_num[PCI_NUM_PINS]; 102 uint32_t first_slot; 103 uint32_t first_pin_irq; 104 AddressSpace bm_as; 105 MemoryRegion bm; 106 /* mmio maps */ 107 MemoryRegion container; 108 MemoryRegion iomem; 109 MemoryRegion pio; 110 MemoryRegion busmem; 111 }; 112 113 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" 114 #define PPC_E500_PCI_BRIDGE(obj) \ 115 OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE) 116 117 struct PPCE500PCIBridgeState { 118 /*< private >*/ 119 PCIDevice parent; 120 /*< public >*/ 121 122 MemoryRegion bar0; 123 }; 124 125 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState; 126 typedef struct PPCE500PCIState PPCE500PCIState; 127 128 static uint64_t pci_reg_read4(void *opaque, hwaddr addr, 129 unsigned size) 130 { 131 PPCE500PCIState *pci = opaque; 132 unsigned long win; 133 uint32_t value = 0; 134 int idx; 135 136 win = addr & 0xfe0; 137 138 switch (win) { 139 case PPCE500_PCI_OW1: 140 case PPCE500_PCI_OW2: 141 case PPCE500_PCI_OW3: 142 case PPCE500_PCI_OW4: 143 idx = (addr >> 5) & 0x7; 144 switch (addr & 0x1F) { 145 case PCI_POTAR: 146 value = pci->pob[idx].potar; 147 break; 148 case PCI_POTEAR: 149 value = pci->pob[idx].potear; 150 break; 151 case PCI_POWBAR: 152 value = pci->pob[idx].powbar; 153 break; 154 case PCI_POWAR: 155 value = pci->pob[idx].powar; 156 break; 157 default: 158 break; 159 } 160 break; 161 162 case PPCE500_PCI_IW3: 163 case PPCE500_PCI_IW2: 164 case PPCE500_PCI_IW1: 165 idx = ((addr >> 5) & 0x3) - 1; 166 switch (addr & 0x1F) { 167 case PCI_PITAR: 168 value = pci->pib[idx].pitar; 169 break; 170 case PCI_PIWBAR: 171 value = pci->pib[idx].piwbar; 172 break; 173 case PCI_PIWBEAR: 174 value = pci->pib[idx].piwbear; 175 break; 176 case PCI_PIWAR: 177 value = pci->pib[idx].piwar; 178 break; 179 default: 180 break; 181 }; 182 break; 183 184 case PPCE500_PCI_GASKET_TIMR: 185 value = pci->gasket_time; 186 break; 187 188 default: 189 break; 190 } 191 192 pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, 193 win, addr, value); 194 return value; 195 } 196 197 /* DMA mapping */ 198 static void e500_update_piw(PPCE500PCIState *pci, int idx) 199 { 200 uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; 201 uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; 202 uint64_t war = pci->pib[idx].piwar; 203 uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); 204 MemoryRegion *address_space_mem = get_system_memory(); 205 MemoryRegion *mem = &pci->pib[idx].mem; 206 MemoryRegion *bm = &pci->bm; 207 char *name; 208 209 if (memory_region_is_mapped(mem)) { 210 /* Before we modify anything, unmap and destroy the region */ 211 memory_region_del_subregion(bm, mem); 212 object_unparent(OBJECT(mem)); 213 } 214 215 if (!(war & PIWAR_EN)) { 216 /* Not enabled, nothing to do */ 217 return; 218 } 219 220 name = g_strdup_printf("PCI Inbound Window %d", idx); 221 memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, 222 size); 223 memory_region_add_subregion_overlap(bm, wbar, mem, -1); 224 g_free(name); 225 226 pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n", 227 __func__, size, wbar, tar); 228 } 229 230 /* BAR mapping */ 231 static void e500_update_pow(PPCE500PCIState *pci, int idx) 232 { 233 uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; 234 uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; 235 uint64_t war = pci->pob[idx].powar; 236 uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); 237 MemoryRegion *mem = &pci->pob[idx].mem; 238 MemoryRegion *address_space_mem = get_system_memory(); 239 char *name; 240 241 if (memory_region_is_mapped(mem)) { 242 /* Before we modify anything, unmap and destroy the region */ 243 memory_region_del_subregion(address_space_mem, mem); 244 object_unparent(OBJECT(mem)); 245 } 246 247 if (!(war & PIWAR_EN)) { 248 /* Not enabled, nothing to do */ 249 return; 250 } 251 252 name = g_strdup_printf("PCI Outbound Window %d", idx); 253 memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, 254 size); 255 memory_region_add_subregion(address_space_mem, wbar, mem); 256 g_free(name); 257 258 pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n", 259 __func__, size, wbar, tar); 260 } 261 262 static void pci_reg_write4(void *opaque, hwaddr addr, 263 uint64_t value, unsigned size) 264 { 265 PPCE500PCIState *pci = opaque; 266 unsigned long win; 267 int idx; 268 269 win = addr & 0xfe0; 270 271 pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", 272 __func__, (unsigned)value, win, addr); 273 274 switch (win) { 275 case PPCE500_PCI_OW1: 276 case PPCE500_PCI_OW2: 277 case PPCE500_PCI_OW3: 278 case PPCE500_PCI_OW4: 279 idx = (addr >> 5) & 0x7; 280 switch (addr & 0x1F) { 281 case PCI_POTAR: 282 pci->pob[idx].potar = value; 283 e500_update_pow(pci, idx); 284 break; 285 case PCI_POTEAR: 286 pci->pob[idx].potear = value; 287 e500_update_pow(pci, idx); 288 break; 289 case PCI_POWBAR: 290 pci->pob[idx].powbar = value; 291 e500_update_pow(pci, idx); 292 break; 293 case PCI_POWAR: 294 pci->pob[idx].powar = value; 295 e500_update_pow(pci, idx); 296 break; 297 default: 298 break; 299 }; 300 break; 301 302 case PPCE500_PCI_IW3: 303 case PPCE500_PCI_IW2: 304 case PPCE500_PCI_IW1: 305 idx = ((addr >> 5) & 0x3) - 1; 306 switch (addr & 0x1F) { 307 case PCI_PITAR: 308 pci->pib[idx].pitar = value; 309 e500_update_piw(pci, idx); 310 break; 311 case PCI_PIWBAR: 312 pci->pib[idx].piwbar = value; 313 e500_update_piw(pci, idx); 314 break; 315 case PCI_PIWBEAR: 316 pci->pib[idx].piwbear = value; 317 e500_update_piw(pci, idx); 318 break; 319 case PCI_PIWAR: 320 pci->pib[idx].piwar = value; 321 e500_update_piw(pci, idx); 322 break; 323 default: 324 break; 325 }; 326 break; 327 328 case PPCE500_PCI_GASKET_TIMR: 329 pci->gasket_time = value; 330 break; 331 332 default: 333 break; 334 }; 335 } 336 337 static const MemoryRegionOps e500_pci_reg_ops = { 338 .read = pci_reg_read4, 339 .write = pci_reg_write4, 340 .endianness = DEVICE_BIG_ENDIAN, 341 }; 342 343 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) 344 { 345 int devno = pci_dev->devfn >> 3; 346 int ret; 347 348 ret = ppce500_pci_map_irq_slot(devno, pin); 349 350 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, 351 pci_dev->devfn, pin, ret, devno); 352 353 return ret; 354 } 355 356 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) 357 { 358 PPCE500PCIState *s = opaque; 359 qemu_irq *pic = s->irq; 360 361 pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); 362 363 qemu_set_irq(pic[pin], level); 364 } 365 366 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin) 367 { 368 PCIINTxRoute route; 369 PPCE500PCIState *s = opaque; 370 371 route.mode = PCI_INTX_ENABLED; 372 route.irq = s->irq_num[pin]; 373 374 pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); 375 return route; 376 } 377 378 static const VMStateDescription vmstate_pci_outbound = { 379 .name = "pci_outbound", 380 .version_id = 0, 381 .minimum_version_id = 0, 382 .fields = (VMStateField[]) { 383 VMSTATE_UINT32(potar, struct pci_outbound), 384 VMSTATE_UINT32(potear, struct pci_outbound), 385 VMSTATE_UINT32(powbar, struct pci_outbound), 386 VMSTATE_UINT32(powar, struct pci_outbound), 387 VMSTATE_END_OF_LIST() 388 } 389 }; 390 391 static const VMStateDescription vmstate_pci_inbound = { 392 .name = "pci_inbound", 393 .version_id = 0, 394 .minimum_version_id = 0, 395 .fields = (VMStateField[]) { 396 VMSTATE_UINT32(pitar, struct pci_inbound), 397 VMSTATE_UINT32(piwbar, struct pci_inbound), 398 VMSTATE_UINT32(piwbear, struct pci_inbound), 399 VMSTATE_UINT32(piwar, struct pci_inbound), 400 VMSTATE_END_OF_LIST() 401 } 402 }; 403 404 static const VMStateDescription vmstate_ppce500_pci = { 405 .name = "ppce500_pci", 406 .version_id = 1, 407 .minimum_version_id = 1, 408 .fields = (VMStateField[]) { 409 VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, 410 vmstate_pci_outbound, struct pci_outbound), 411 VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, 412 vmstate_pci_inbound, struct pci_inbound), 413 VMSTATE_UINT32(gasket_time, PPCE500PCIState), 414 VMSTATE_END_OF_LIST() 415 } 416 }; 417 418 #include "exec/address-spaces.h" 419 420 static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) 421 { 422 PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); 423 PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), 424 "/e500-ccsr")); 425 426 memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, 427 0, int128_get64(ccsr->ccsr_space.size)); 428 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); 429 } 430 431 static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque, 432 int devfn) 433 { 434 PPCE500PCIState *s = opaque; 435 436 return &s->bm_as; 437 } 438 439 static void e500_pcihost_realize(DeviceState *dev, Error **errp) 440 { 441 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 442 PCIHostState *h; 443 PPCE500PCIState *s; 444 PCIBus *b; 445 int i; 446 447 h = PCI_HOST_BRIDGE(dev); 448 s = PPC_E500_PCI_HOST_BRIDGE(dev); 449 450 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 451 sysbus_init_irq(sbd, &s->irq[i]); 452 } 453 454 for (i = 0; i < PCI_NUM_PINS; i++) { 455 s->irq_num[i] = s->first_pin_irq + i; 456 } 457 458 memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); 459 memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); 460 461 /* PIO lives at the bottom of our bus space */ 462 memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2); 463 464 b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq, 465 mpc85xx_pci_map_irq, s, &s->busmem, &s->pio, 466 PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); 467 h->bus = b; 468 469 /* Set up PCI view of memory */ 470 memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX); 471 memory_region_add_subregion(&s->bm, 0x0, &s->busmem); 472 address_space_init(&s->bm_as, &s->bm, "pci-bm"); 473 pci_setup_iommu(b, e500_pcihost_set_iommu, s); 474 475 pci_create_simple(b, 0, "e500-host-bridge"); 476 477 memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); 478 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, 479 "pci-conf-idx", 4); 480 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h, 481 "pci-conf-data", 4); 482 memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s, 483 "pci.reg", PCIE500_REG_SIZE); 484 memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); 485 memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); 486 memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); 487 sysbus_init_mmio(sbd, &s->container); 488 pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); 489 } 490 491 static void e500_host_bridge_class_init(ObjectClass *klass, void *data) 492 { 493 DeviceClass *dc = DEVICE_CLASS(klass); 494 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 495 496 k->realize = e500_pcihost_bridge_realize; 497 k->vendor_id = PCI_VENDOR_ID_FREESCALE; 498 k->device_id = PCI_DEVICE_ID_MPC8533E; 499 k->class_id = PCI_CLASS_PROCESSOR_POWERPC; 500 dc->desc = "Host bridge"; 501 /* 502 * PCI-facing part of the host bridge, not usable without the 503 * host-facing part, which can't be device_add'ed, yet. 504 */ 505 dc->user_creatable = false; 506 } 507 508 static const TypeInfo e500_host_bridge_info = { 509 .name = "e500-host-bridge", 510 .parent = TYPE_PCI_DEVICE, 511 .instance_size = sizeof(PPCE500PCIBridgeState), 512 .class_init = e500_host_bridge_class_init, 513 .interfaces = (InterfaceInfo[]) { 514 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 515 { }, 516 }, 517 }; 518 519 static Property pcihost_properties[] = { 520 DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), 521 DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1), 522 DEFINE_PROP_END_OF_LIST(), 523 }; 524 525 static void e500_pcihost_class_init(ObjectClass *klass, void *data) 526 { 527 DeviceClass *dc = DEVICE_CLASS(klass); 528 529 dc->realize = e500_pcihost_realize; 530 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 531 dc->props = pcihost_properties; 532 dc->vmsd = &vmstate_ppce500_pci; 533 } 534 535 static const TypeInfo e500_pcihost_info = { 536 .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, 537 .parent = TYPE_PCI_HOST_BRIDGE, 538 .instance_size = sizeof(PPCE500PCIState), 539 .class_init = e500_pcihost_class_init, 540 }; 541 542 static void e500_pci_register_types(void) 543 { 544 type_register_static(&e500_pcihost_info); 545 type_register_static(&e500_host_bridge_info); 546 } 547 548 type_init(e500_pci_register_types) 549