1 /* 2 * QEMU PowerPC E500 embedded processors pci controller emulation 3 * 4 * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5 * 6 * Author: Yu Liu, <yu.liu@freescale.com> 7 * 8 * This file is derived from hw/ppc4xx_pci.c, 9 * the copyright for that material belongs to the original owners. 10 * 11 * This is free software; you can redistribute it and/or modify 12 * it under the terms of the GNU General Public License as published by 13 * the Free Software Foundation; either version 2 of the License, or 14 * (at your option) any later version. 15 */ 16 17 #include "hw/hw.h" 18 #include "hw/ppc/e500-ccsr.h" 19 #include "hw/pci/pci.h" 20 #include "hw/pci/pci_host.h" 21 #include "qemu/bswap.h" 22 #include "hw/pci-host/ppce500.h" 23 24 #ifdef DEBUG_PCI 25 #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) 26 #else 27 #define pci_debug(fmt, ...) 28 #endif 29 30 #define PCIE500_CFGADDR 0x0 31 #define PCIE500_CFGDATA 0x4 32 #define PCIE500_REG_BASE 0xC00 33 #define PCIE500_ALL_SIZE 0x1000 34 #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) 35 36 #define PCIE500_PCI_IOLEN 0x10000ULL 37 38 #define PPCE500_PCI_CONFIG_ADDR 0x0 39 #define PPCE500_PCI_CONFIG_DATA 0x4 40 #define PPCE500_PCI_INTACK 0x8 41 42 #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) 43 #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) 44 #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) 45 #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) 46 #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) 47 #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) 48 #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) 49 50 #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) 51 52 #define PCI_POTAR 0x0 53 #define PCI_POTEAR 0x4 54 #define PCI_POWBAR 0x8 55 #define PCI_POWAR 0x10 56 57 #define PCI_PITAR 0x0 58 #define PCI_PIWBAR 0x8 59 #define PCI_PIWBEAR 0xC 60 #define PCI_PIWAR 0x10 61 62 #define PPCE500_PCI_NR_POBS 5 63 #define PPCE500_PCI_NR_PIBS 3 64 65 struct pci_outbound { 66 uint32_t potar; 67 uint32_t potear; 68 uint32_t powbar; 69 uint32_t powar; 70 }; 71 72 struct pci_inbound { 73 uint32_t pitar; 74 uint32_t piwbar; 75 uint32_t piwbear; 76 uint32_t piwar; 77 }; 78 79 #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" 80 81 #define PPC_E500_PCI_HOST_BRIDGE(obj) \ 82 OBJECT_CHECK(PPCE500PCIState, (obj), TYPE_PPC_E500_PCI_HOST_BRIDGE) 83 84 struct PPCE500PCIState { 85 PCIHostState parent_obj; 86 87 struct pci_outbound pob[PPCE500_PCI_NR_POBS]; 88 struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; 89 uint32_t gasket_time; 90 qemu_irq irq[PCI_NUM_PINS]; 91 uint32_t irq_num[PCI_NUM_PINS]; 92 uint32_t first_slot; 93 uint32_t first_pin_irq; 94 /* mmio maps */ 95 MemoryRegion container; 96 MemoryRegion iomem; 97 MemoryRegion pio; 98 }; 99 100 #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" 101 #define PPC_E500_PCI_BRIDGE(obj) \ 102 OBJECT_CHECK(PPCE500PCIBridgeState, (obj), TYPE_PPC_E500_PCI_BRIDGE) 103 104 struct PPCE500PCIBridgeState { 105 /*< private >*/ 106 PCIDevice parent; 107 /*< public >*/ 108 109 MemoryRegion bar0; 110 }; 111 112 typedef struct PPCE500PCIBridgeState PPCE500PCIBridgeState; 113 typedef struct PPCE500PCIState PPCE500PCIState; 114 115 static uint64_t pci_reg_read4(void *opaque, hwaddr addr, 116 unsigned size) 117 { 118 PPCE500PCIState *pci = opaque; 119 unsigned long win; 120 uint32_t value = 0; 121 int idx; 122 123 win = addr & 0xfe0; 124 125 switch (win) { 126 case PPCE500_PCI_OW1: 127 case PPCE500_PCI_OW2: 128 case PPCE500_PCI_OW3: 129 case PPCE500_PCI_OW4: 130 idx = (addr >> 5) & 0x7; 131 switch (addr & 0xC) { 132 case PCI_POTAR: 133 value = pci->pob[idx].potar; 134 break; 135 case PCI_POTEAR: 136 value = pci->pob[idx].potear; 137 break; 138 case PCI_POWBAR: 139 value = pci->pob[idx].powbar; 140 break; 141 case PCI_POWAR: 142 value = pci->pob[idx].powar; 143 break; 144 default: 145 break; 146 } 147 break; 148 149 case PPCE500_PCI_IW3: 150 case PPCE500_PCI_IW2: 151 case PPCE500_PCI_IW1: 152 idx = ((addr >> 5) & 0x3) - 1; 153 switch (addr & 0xC) { 154 case PCI_PITAR: 155 value = pci->pib[idx].pitar; 156 break; 157 case PCI_PIWBAR: 158 value = pci->pib[idx].piwbar; 159 break; 160 case PCI_PIWBEAR: 161 value = pci->pib[idx].piwbear; 162 break; 163 case PCI_PIWAR: 164 value = pci->pib[idx].piwar; 165 break; 166 default: 167 break; 168 }; 169 break; 170 171 case PPCE500_PCI_GASKET_TIMR: 172 value = pci->gasket_time; 173 break; 174 175 default: 176 break; 177 } 178 179 pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, 180 win, addr, value); 181 return value; 182 } 183 184 static void pci_reg_write4(void *opaque, hwaddr addr, 185 uint64_t value, unsigned size) 186 { 187 PPCE500PCIState *pci = opaque; 188 unsigned long win; 189 int idx; 190 191 win = addr & 0xfe0; 192 193 pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", 194 __func__, (unsigned)value, win, addr); 195 196 switch (win) { 197 case PPCE500_PCI_OW1: 198 case PPCE500_PCI_OW2: 199 case PPCE500_PCI_OW3: 200 case PPCE500_PCI_OW4: 201 idx = (addr >> 5) & 0x7; 202 switch (addr & 0xC) { 203 case PCI_POTAR: 204 pci->pob[idx].potar = value; 205 break; 206 case PCI_POTEAR: 207 pci->pob[idx].potear = value; 208 break; 209 case PCI_POWBAR: 210 pci->pob[idx].powbar = value; 211 break; 212 case PCI_POWAR: 213 pci->pob[idx].powar = value; 214 break; 215 default: 216 break; 217 }; 218 break; 219 220 case PPCE500_PCI_IW3: 221 case PPCE500_PCI_IW2: 222 case PPCE500_PCI_IW1: 223 idx = ((addr >> 5) & 0x3) - 1; 224 switch (addr & 0xC) { 225 case PCI_PITAR: 226 pci->pib[idx].pitar = value; 227 break; 228 case PCI_PIWBAR: 229 pci->pib[idx].piwbar = value; 230 break; 231 case PCI_PIWBEAR: 232 pci->pib[idx].piwbear = value; 233 break; 234 case PCI_PIWAR: 235 pci->pib[idx].piwar = value; 236 break; 237 default: 238 break; 239 }; 240 break; 241 242 case PPCE500_PCI_GASKET_TIMR: 243 pci->gasket_time = value; 244 break; 245 246 default: 247 break; 248 }; 249 } 250 251 static const MemoryRegionOps e500_pci_reg_ops = { 252 .read = pci_reg_read4, 253 .write = pci_reg_write4, 254 .endianness = DEVICE_BIG_ENDIAN, 255 }; 256 257 static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) 258 { 259 int devno = pci_dev->devfn >> 3; 260 int ret; 261 262 ret = ppce500_pci_map_irq_slot(devno, pin); 263 264 pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, 265 pci_dev->devfn, pin, ret, devno); 266 267 return ret; 268 } 269 270 static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) 271 { 272 PPCE500PCIState *s = opaque; 273 qemu_irq *pic = s->irq; 274 275 pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); 276 277 qemu_set_irq(pic[pin], level); 278 } 279 280 static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin) 281 { 282 PCIINTxRoute route; 283 PPCE500PCIState *s = opaque; 284 285 route.mode = PCI_INTX_ENABLED; 286 route.irq = s->irq_num[pin]; 287 288 pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); 289 return route; 290 } 291 292 static const VMStateDescription vmstate_pci_outbound = { 293 .name = "pci_outbound", 294 .version_id = 0, 295 .minimum_version_id = 0, 296 .fields = (VMStateField[]) { 297 VMSTATE_UINT32(potar, struct pci_outbound), 298 VMSTATE_UINT32(potear, struct pci_outbound), 299 VMSTATE_UINT32(powbar, struct pci_outbound), 300 VMSTATE_UINT32(powar, struct pci_outbound), 301 VMSTATE_END_OF_LIST() 302 } 303 }; 304 305 static const VMStateDescription vmstate_pci_inbound = { 306 .name = "pci_inbound", 307 .version_id = 0, 308 .minimum_version_id = 0, 309 .fields = (VMStateField[]) { 310 VMSTATE_UINT32(pitar, struct pci_inbound), 311 VMSTATE_UINT32(piwbar, struct pci_inbound), 312 VMSTATE_UINT32(piwbear, struct pci_inbound), 313 VMSTATE_UINT32(piwar, struct pci_inbound), 314 VMSTATE_END_OF_LIST() 315 } 316 }; 317 318 static const VMStateDescription vmstate_ppce500_pci = { 319 .name = "ppce500_pci", 320 .version_id = 1, 321 .minimum_version_id = 1, 322 .fields = (VMStateField[]) { 323 VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, 324 vmstate_pci_outbound, struct pci_outbound), 325 VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, 326 vmstate_pci_inbound, struct pci_inbound), 327 VMSTATE_UINT32(gasket_time, PPCE500PCIState), 328 VMSTATE_END_OF_LIST() 329 } 330 }; 331 332 #include "exec/address-spaces.h" 333 334 static int e500_pcihost_bridge_initfn(PCIDevice *d) 335 { 336 PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); 337 PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), 338 "/e500-ccsr")); 339 340 pci_config_set_class(d->config, PCI_CLASS_BRIDGE_PCI); 341 d->config[PCI_HEADER_TYPE] = 342 (d->config[PCI_HEADER_TYPE] & PCI_HEADER_TYPE_MULTI_FUNCTION) | 343 PCI_HEADER_TYPE_BRIDGE; 344 345 memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, 346 0, int128_get64(ccsr->ccsr_space.size)); 347 pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); 348 349 return 0; 350 } 351 352 static int e500_pcihost_initfn(SysBusDevice *dev) 353 { 354 PCIHostState *h; 355 PPCE500PCIState *s; 356 PCIBus *b; 357 int i; 358 MemoryRegion *address_space_mem = get_system_memory(); 359 360 h = PCI_HOST_BRIDGE(dev); 361 s = PPC_E500_PCI_HOST_BRIDGE(dev); 362 363 for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 364 sysbus_init_irq(dev, &s->irq[i]); 365 } 366 367 for (i = 0; i < PCI_NUM_PINS; i++) { 368 s->irq_num[i] = s->first_pin_irq + i; 369 } 370 371 memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); 372 373 b = pci_register_bus(DEVICE(dev), NULL, mpc85xx_pci_set_irq, 374 mpc85xx_pci_map_irq, s, address_space_mem, 375 &s->pio, PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); 376 h->bus = b; 377 378 pci_create_simple(b, 0, "e500-host-bridge"); 379 380 memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); 381 memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, 382 "pci-conf-idx", 4); 383 memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h, 384 "pci-conf-data", 4); 385 memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s, 386 "pci.reg", PCIE500_REG_SIZE); 387 memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); 388 memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); 389 memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); 390 sysbus_init_mmio(dev, &s->container); 391 sysbus_init_mmio(dev, &s->pio); 392 pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); 393 394 return 0; 395 } 396 397 static void e500_host_bridge_class_init(ObjectClass *klass, void *data) 398 { 399 DeviceClass *dc = DEVICE_CLASS(klass); 400 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 401 402 k->init = e500_pcihost_bridge_initfn; 403 k->vendor_id = PCI_VENDOR_ID_FREESCALE; 404 k->device_id = PCI_DEVICE_ID_MPC8533E; 405 k->class_id = PCI_CLASS_PROCESSOR_POWERPC; 406 dc->desc = "Host bridge"; 407 /* 408 * PCI-facing part of the host bridge, not usable without the 409 * host-facing part, which can't be device_add'ed, yet. 410 */ 411 dc->cannot_instantiate_with_device_add_yet = true; 412 } 413 414 static const TypeInfo e500_host_bridge_info = { 415 .name = "e500-host-bridge", 416 .parent = TYPE_PCI_DEVICE, 417 .instance_size = sizeof(PPCE500PCIBridgeState), 418 .class_init = e500_host_bridge_class_init, 419 }; 420 421 static Property pcihost_properties[] = { 422 DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), 423 DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1), 424 DEFINE_PROP_END_OF_LIST(), 425 }; 426 427 static void e500_pcihost_class_init(ObjectClass *klass, void *data) 428 { 429 DeviceClass *dc = DEVICE_CLASS(klass); 430 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 431 432 k->init = e500_pcihost_initfn; 433 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 434 dc->props = pcihost_properties; 435 dc->vmsd = &vmstate_ppce500_pci; 436 } 437 438 static const TypeInfo e500_pcihost_info = { 439 .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, 440 .parent = TYPE_PCI_HOST_BRIDGE, 441 .instance_size = sizeof(PPCE500PCIState), 442 .class_init = e500_pcihost_class_init, 443 }; 444 445 static void e500_pci_register_types(void) 446 { 447 type_register_static(&e500_pcihost_info); 448 type_register_static(&e500_host_bridge_info); 449 } 450 451 type_init(e500_pci_register_types) 452