1c0907c9eSPaolo Bonzini /* 2c0907c9eSPaolo Bonzini * QEMU PowerPC E500 embedded processors pci controller emulation 3c0907c9eSPaolo Bonzini * 4c0907c9eSPaolo Bonzini * Copyright (C) 2009 Freescale Semiconductor, Inc. All rights reserved. 5c0907c9eSPaolo Bonzini * 6c0907c9eSPaolo Bonzini * Author: Yu Liu, <yu.liu@freescale.com> 7c0907c9eSPaolo Bonzini * 8c0907c9eSPaolo Bonzini * This file is derived from hw/ppc4xx_pci.c, 9c0907c9eSPaolo Bonzini * the copyright for that material belongs to the original owners. 10c0907c9eSPaolo Bonzini * 11c0907c9eSPaolo Bonzini * This is free software; you can redistribute it and/or modify 12c0907c9eSPaolo Bonzini * it under the terms of the GNU General Public License as published by 13c0907c9eSPaolo Bonzini * the Free Software Foundation; either version 2 of the License, or 14c0907c9eSPaolo Bonzini * (at your option) any later version. 15c0907c9eSPaolo Bonzini */ 16c0907c9eSPaolo Bonzini 1797d5408fSPeter Maydell #include "qemu/osdep.h" 1864552b6bSMarkus Armbruster #include "hw/irq.h" 19c0907c9eSPaolo Bonzini #include "hw/ppc/e500-ccsr.h" 20a27bd6c7SMarkus Armbruster #include "hw/qdev-properties.h" 21d6454270SMarkus Armbruster #include "migration/vmstate.h" 22c0907c9eSPaolo Bonzini #include "hw/pci/pci.h" 23c0907c9eSPaolo Bonzini #include "hw/pci/pci_host.h" 24c0907c9eSPaolo Bonzini #include "qemu/bswap.h" 250b8fa32fSMarkus Armbruster #include "qemu/module.h" 26c0907c9eSPaolo Bonzini #include "hw/pci-host/ppce500.h" 27db1015e9SEduardo Habkost #include "qom/object.h" 28c0907c9eSPaolo Bonzini 29c0907c9eSPaolo Bonzini #ifdef DEBUG_PCI 30c0907c9eSPaolo Bonzini #define pci_debug(fmt, ...) fprintf(stderr, fmt, ## __VA_ARGS__) 31c0907c9eSPaolo Bonzini #else 32c0907c9eSPaolo Bonzini #define pci_debug(fmt, ...) 33c0907c9eSPaolo Bonzini #endif 34c0907c9eSPaolo Bonzini 35c0907c9eSPaolo Bonzini #define PCIE500_CFGADDR 0x0 36c0907c9eSPaolo Bonzini #define PCIE500_CFGDATA 0x4 37c0907c9eSPaolo Bonzini #define PCIE500_REG_BASE 0xC00 38c0907c9eSPaolo Bonzini #define PCIE500_ALL_SIZE 0x1000 39c0907c9eSPaolo Bonzini #define PCIE500_REG_SIZE (PCIE500_ALL_SIZE - PCIE500_REG_BASE) 40c0907c9eSPaolo Bonzini 41c0907c9eSPaolo Bonzini #define PCIE500_PCI_IOLEN 0x10000ULL 42c0907c9eSPaolo Bonzini 43c0907c9eSPaolo Bonzini #define PPCE500_PCI_CONFIG_ADDR 0x0 44c0907c9eSPaolo Bonzini #define PPCE500_PCI_CONFIG_DATA 0x4 45c0907c9eSPaolo Bonzini #define PPCE500_PCI_INTACK 0x8 46c0907c9eSPaolo Bonzini 47c0907c9eSPaolo Bonzini #define PPCE500_PCI_OW1 (0xC20 - PCIE500_REG_BASE) 48c0907c9eSPaolo Bonzini #define PPCE500_PCI_OW2 (0xC40 - PCIE500_REG_BASE) 49c0907c9eSPaolo Bonzini #define PPCE500_PCI_OW3 (0xC60 - PCIE500_REG_BASE) 50c0907c9eSPaolo Bonzini #define PPCE500_PCI_OW4 (0xC80 - PCIE500_REG_BASE) 51c0907c9eSPaolo Bonzini #define PPCE500_PCI_IW3 (0xDA0 - PCIE500_REG_BASE) 52c0907c9eSPaolo Bonzini #define PPCE500_PCI_IW2 (0xDC0 - PCIE500_REG_BASE) 53c0907c9eSPaolo Bonzini #define PPCE500_PCI_IW1 (0xDE0 - PCIE500_REG_BASE) 54c0907c9eSPaolo Bonzini 55c0907c9eSPaolo Bonzini #define PPCE500_PCI_GASKET_TIMR (0xE20 - PCIE500_REG_BASE) 56c0907c9eSPaolo Bonzini 57c0907c9eSPaolo Bonzini #define PCI_POTAR 0x0 58c0907c9eSPaolo Bonzini #define PCI_POTEAR 0x4 59c0907c9eSPaolo Bonzini #define PCI_POWBAR 0x8 60c0907c9eSPaolo Bonzini #define PCI_POWAR 0x10 61c0907c9eSPaolo Bonzini 62c0907c9eSPaolo Bonzini #define PCI_PITAR 0x0 63c0907c9eSPaolo Bonzini #define PCI_PIWBAR 0x8 64c0907c9eSPaolo Bonzini #define PCI_PIWBEAR 0xC 65c0907c9eSPaolo Bonzini #define PCI_PIWAR 0x10 66c0907c9eSPaolo Bonzini 67c0907c9eSPaolo Bonzini #define PPCE500_PCI_NR_POBS 5 68c0907c9eSPaolo Bonzini #define PPCE500_PCI_NR_PIBS 3 69c0907c9eSPaolo Bonzini 70cb3778a0SAlexander Graf #define PIWAR_EN 0x80000000 /* Enable */ 71cb3778a0SAlexander Graf #define PIWAR_PF 0x20000000 /* prefetch */ 72cb3778a0SAlexander Graf #define PIWAR_TGI_LOCAL 0x00f00000 /* target - local memory */ 73cb3778a0SAlexander Graf #define PIWAR_READ_SNOOP 0x00050000 74cb3778a0SAlexander Graf #define PIWAR_WRITE_SNOOP 0x00005000 75cb3778a0SAlexander Graf #define PIWAR_SZ_MASK 0x0000003f 76cb3778a0SAlexander Graf 77c0907c9eSPaolo Bonzini struct pci_outbound { 78c0907c9eSPaolo Bonzini uint32_t potar; 79c0907c9eSPaolo Bonzini uint32_t potear; 80c0907c9eSPaolo Bonzini uint32_t powbar; 81c0907c9eSPaolo Bonzini uint32_t powar; 82cb3778a0SAlexander Graf MemoryRegion mem; 83c0907c9eSPaolo Bonzini }; 84c0907c9eSPaolo Bonzini 85c0907c9eSPaolo Bonzini struct pci_inbound { 86c0907c9eSPaolo Bonzini uint32_t pitar; 87c0907c9eSPaolo Bonzini uint32_t piwbar; 88c0907c9eSPaolo Bonzini uint32_t piwbear; 89c0907c9eSPaolo Bonzini uint32_t piwar; 90cb3778a0SAlexander Graf MemoryRegion mem; 91c0907c9eSPaolo Bonzini }; 92c0907c9eSPaolo Bonzini 93c0907c9eSPaolo Bonzini #define TYPE_PPC_E500_PCI_HOST_BRIDGE "e500-pcihost" 94c0907c9eSPaolo Bonzini 958063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIState, PPC_E500_PCI_HOST_BRIDGE) 96c0907c9eSPaolo Bonzini 97c0907c9eSPaolo Bonzini struct PPCE500PCIState { 98c0907c9eSPaolo Bonzini PCIHostState parent_obj; 99c0907c9eSPaolo Bonzini 100c0907c9eSPaolo Bonzini struct pci_outbound pob[PPCE500_PCI_NR_POBS]; 101c0907c9eSPaolo Bonzini struct pci_inbound pib[PPCE500_PCI_NR_PIBS]; 102c0907c9eSPaolo Bonzini uint32_t gasket_time; 103d575a6ceSBharat Bhushan qemu_irq irq[PCI_NUM_PINS]; 1043016dca0SBharat Bhushan uint32_t irq_num[PCI_NUM_PINS]; 105c0907c9eSPaolo Bonzini uint32_t first_slot; 1063016dca0SBharat Bhushan uint32_t first_pin_irq; 107cb3778a0SAlexander Graf AddressSpace bm_as; 108cb3778a0SAlexander Graf MemoryRegion bm; 109c0907c9eSPaolo Bonzini /* mmio maps */ 110c0907c9eSPaolo Bonzini MemoryRegion container; 111c0907c9eSPaolo Bonzini MemoryRegion iomem; 112c0907c9eSPaolo Bonzini MemoryRegion pio; 113cb3778a0SAlexander Graf MemoryRegion busmem; 114c0907c9eSPaolo Bonzini }; 115c0907c9eSPaolo Bonzini 116c0907c9eSPaolo Bonzini #define TYPE_PPC_E500_PCI_BRIDGE "e500-host-bridge" 1178063396bSEduardo Habkost OBJECT_DECLARE_SIMPLE_TYPE(PPCE500PCIBridgeState, PPC_E500_PCI_BRIDGE) 118c0907c9eSPaolo Bonzini 119c0907c9eSPaolo Bonzini struct PPCE500PCIBridgeState { 120c0907c9eSPaolo Bonzini /*< private >*/ 121c0907c9eSPaolo Bonzini PCIDevice parent; 122c0907c9eSPaolo Bonzini /*< public >*/ 123c0907c9eSPaolo Bonzini 124c0907c9eSPaolo Bonzini MemoryRegion bar0; 125c0907c9eSPaolo Bonzini }; 126c0907c9eSPaolo Bonzini 127c0907c9eSPaolo Bonzini 128c0907c9eSPaolo Bonzini static uint64_t pci_reg_read4(void *opaque, hwaddr addr, 129c0907c9eSPaolo Bonzini unsigned size) 130c0907c9eSPaolo Bonzini { 131c0907c9eSPaolo Bonzini PPCE500PCIState *pci = opaque; 132c0907c9eSPaolo Bonzini unsigned long win; 133c0907c9eSPaolo Bonzini uint32_t value = 0; 134c0907c9eSPaolo Bonzini int idx; 135c0907c9eSPaolo Bonzini 136c0907c9eSPaolo Bonzini win = addr & 0xfe0; 137c0907c9eSPaolo Bonzini 138c0907c9eSPaolo Bonzini switch (win) { 139c0907c9eSPaolo Bonzini case PPCE500_PCI_OW1: 140c0907c9eSPaolo Bonzini case PPCE500_PCI_OW2: 141c0907c9eSPaolo Bonzini case PPCE500_PCI_OW3: 142c0907c9eSPaolo Bonzini case PPCE500_PCI_OW4: 143c0907c9eSPaolo Bonzini idx = (addr >> 5) & 0x7; 144e7f08320SRudolf Marek switch (addr & 0x1F) { 145c0907c9eSPaolo Bonzini case PCI_POTAR: 146c0907c9eSPaolo Bonzini value = pci->pob[idx].potar; 147c0907c9eSPaolo Bonzini break; 148c0907c9eSPaolo Bonzini case PCI_POTEAR: 149c0907c9eSPaolo Bonzini value = pci->pob[idx].potear; 150c0907c9eSPaolo Bonzini break; 151c0907c9eSPaolo Bonzini case PCI_POWBAR: 152c0907c9eSPaolo Bonzini value = pci->pob[idx].powbar; 153c0907c9eSPaolo Bonzini break; 154c0907c9eSPaolo Bonzini case PCI_POWAR: 155c0907c9eSPaolo Bonzini value = pci->pob[idx].powar; 156c0907c9eSPaolo Bonzini break; 157c0907c9eSPaolo Bonzini default: 158c0907c9eSPaolo Bonzini break; 159c0907c9eSPaolo Bonzini } 160c0907c9eSPaolo Bonzini break; 161c0907c9eSPaolo Bonzini 162c0907c9eSPaolo Bonzini case PPCE500_PCI_IW3: 163c0907c9eSPaolo Bonzini case PPCE500_PCI_IW2: 164c0907c9eSPaolo Bonzini case PPCE500_PCI_IW1: 165c0907c9eSPaolo Bonzini idx = ((addr >> 5) & 0x3) - 1; 166e7f08320SRudolf Marek switch (addr & 0x1F) { 167c0907c9eSPaolo Bonzini case PCI_PITAR: 168c0907c9eSPaolo Bonzini value = pci->pib[idx].pitar; 169c0907c9eSPaolo Bonzini break; 170c0907c9eSPaolo Bonzini case PCI_PIWBAR: 171c0907c9eSPaolo Bonzini value = pci->pib[idx].piwbar; 172c0907c9eSPaolo Bonzini break; 173c0907c9eSPaolo Bonzini case PCI_PIWBEAR: 174c0907c9eSPaolo Bonzini value = pci->pib[idx].piwbear; 175c0907c9eSPaolo Bonzini break; 176c0907c9eSPaolo Bonzini case PCI_PIWAR: 177c0907c9eSPaolo Bonzini value = pci->pib[idx].piwar; 178c0907c9eSPaolo Bonzini break; 179c0907c9eSPaolo Bonzini default: 180c0907c9eSPaolo Bonzini break; 181c0907c9eSPaolo Bonzini }; 182c0907c9eSPaolo Bonzini break; 183c0907c9eSPaolo Bonzini 184c0907c9eSPaolo Bonzini case PPCE500_PCI_GASKET_TIMR: 185c0907c9eSPaolo Bonzini value = pci->gasket_time; 186c0907c9eSPaolo Bonzini break; 187c0907c9eSPaolo Bonzini 188c0907c9eSPaolo Bonzini default: 189c0907c9eSPaolo Bonzini break; 190c0907c9eSPaolo Bonzini } 191c0907c9eSPaolo Bonzini 192c0907c9eSPaolo Bonzini pci_debug("%s: win:%lx(addr:" TARGET_FMT_plx ") -> value:%x\n", __func__, 193c0907c9eSPaolo Bonzini win, addr, value); 194c0907c9eSPaolo Bonzini return value; 195c0907c9eSPaolo Bonzini } 196c0907c9eSPaolo Bonzini 197cb3778a0SAlexander Graf /* DMA mapping */ 198cb3778a0SAlexander Graf static void e500_update_piw(PPCE500PCIState *pci, int idx) 199cb3778a0SAlexander Graf { 200cb3778a0SAlexander Graf uint64_t tar = ((uint64_t)pci->pib[idx].pitar) << 12; 201cb3778a0SAlexander Graf uint64_t wbar = ((uint64_t)pci->pib[idx].piwbar) << 12; 202cb3778a0SAlexander Graf uint64_t war = pci->pib[idx].piwar; 203cb3778a0SAlexander Graf uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); 204cb3778a0SAlexander Graf MemoryRegion *address_space_mem = get_system_memory(); 205cb3778a0SAlexander Graf MemoryRegion *mem = &pci->pib[idx].mem; 206cb3778a0SAlexander Graf MemoryRegion *bm = &pci->bm; 207cb3778a0SAlexander Graf char *name; 208cb3778a0SAlexander Graf 209cb3778a0SAlexander Graf if (memory_region_is_mapped(mem)) { 210cb3778a0SAlexander Graf /* Before we modify anything, unmap and destroy the region */ 211cb3778a0SAlexander Graf memory_region_del_subregion(bm, mem); 212cb3778a0SAlexander Graf object_unparent(OBJECT(mem)); 213cb3778a0SAlexander Graf } 214cb3778a0SAlexander Graf 215cb3778a0SAlexander Graf if (!(war & PIWAR_EN)) { 216cb3778a0SAlexander Graf /* Not enabled, nothing to do */ 217cb3778a0SAlexander Graf return; 218cb3778a0SAlexander Graf } 219cb3778a0SAlexander Graf 220cb3778a0SAlexander Graf name = g_strdup_printf("PCI Inbound Window %d", idx); 221cb3778a0SAlexander Graf memory_region_init_alias(mem, OBJECT(pci), name, address_space_mem, tar, 222cb3778a0SAlexander Graf size); 223cb3778a0SAlexander Graf memory_region_add_subregion_overlap(bm, wbar, mem, -1); 224cb3778a0SAlexander Graf g_free(name); 225cb3778a0SAlexander Graf 226cb3778a0SAlexander Graf pci_debug("%s: Added window of size=%#lx from PCI=%#lx to CPU=%#lx\n", 227cb3778a0SAlexander Graf __func__, size, wbar, tar); 228cb3778a0SAlexander Graf } 229cb3778a0SAlexander Graf 230cb3778a0SAlexander Graf /* BAR mapping */ 231cb3778a0SAlexander Graf static void e500_update_pow(PPCE500PCIState *pci, int idx) 232cb3778a0SAlexander Graf { 233cb3778a0SAlexander Graf uint64_t tar = ((uint64_t)pci->pob[idx].potar) << 12; 234cb3778a0SAlexander Graf uint64_t wbar = ((uint64_t)pci->pob[idx].powbar) << 12; 235cb3778a0SAlexander Graf uint64_t war = pci->pob[idx].powar; 236cb3778a0SAlexander Graf uint64_t size = 2ULL << (war & PIWAR_SZ_MASK); 237cb3778a0SAlexander Graf MemoryRegion *mem = &pci->pob[idx].mem; 238cb3778a0SAlexander Graf MemoryRegion *address_space_mem = get_system_memory(); 239cb3778a0SAlexander Graf char *name; 240cb3778a0SAlexander Graf 241cb3778a0SAlexander Graf if (memory_region_is_mapped(mem)) { 242cb3778a0SAlexander Graf /* Before we modify anything, unmap and destroy the region */ 243cb3778a0SAlexander Graf memory_region_del_subregion(address_space_mem, mem); 244cb3778a0SAlexander Graf object_unparent(OBJECT(mem)); 245cb3778a0SAlexander Graf } 246cb3778a0SAlexander Graf 247cb3778a0SAlexander Graf if (!(war & PIWAR_EN)) { 248cb3778a0SAlexander Graf /* Not enabled, nothing to do */ 249cb3778a0SAlexander Graf return; 250cb3778a0SAlexander Graf } 251cb3778a0SAlexander Graf 252cb3778a0SAlexander Graf name = g_strdup_printf("PCI Outbound Window %d", idx); 253cb3778a0SAlexander Graf memory_region_init_alias(mem, OBJECT(pci), name, &pci->busmem, tar, 254cb3778a0SAlexander Graf size); 255cb3778a0SAlexander Graf memory_region_add_subregion(address_space_mem, wbar, mem); 256cb3778a0SAlexander Graf g_free(name); 257cb3778a0SAlexander Graf 258cb3778a0SAlexander Graf pci_debug("%s: Added window of size=%#lx from CPU=%#lx to PCI=%#lx\n", 259cb3778a0SAlexander Graf __func__, size, wbar, tar); 260cb3778a0SAlexander Graf } 261cb3778a0SAlexander Graf 262c0907c9eSPaolo Bonzini static void pci_reg_write4(void *opaque, hwaddr addr, 263c0907c9eSPaolo Bonzini uint64_t value, unsigned size) 264c0907c9eSPaolo Bonzini { 265c0907c9eSPaolo Bonzini PPCE500PCIState *pci = opaque; 266c0907c9eSPaolo Bonzini unsigned long win; 267c0907c9eSPaolo Bonzini int idx; 268c0907c9eSPaolo Bonzini 269c0907c9eSPaolo Bonzini win = addr & 0xfe0; 270c0907c9eSPaolo Bonzini 271c0907c9eSPaolo Bonzini pci_debug("%s: value:%x -> win:%lx(addr:" TARGET_FMT_plx ")\n", 272c0907c9eSPaolo Bonzini __func__, (unsigned)value, win, addr); 273c0907c9eSPaolo Bonzini 274c0907c9eSPaolo Bonzini switch (win) { 275c0907c9eSPaolo Bonzini case PPCE500_PCI_OW1: 276c0907c9eSPaolo Bonzini case PPCE500_PCI_OW2: 277c0907c9eSPaolo Bonzini case PPCE500_PCI_OW3: 278c0907c9eSPaolo Bonzini case PPCE500_PCI_OW4: 279c0907c9eSPaolo Bonzini idx = (addr >> 5) & 0x7; 280cb3778a0SAlexander Graf switch (addr & 0x1F) { 281c0907c9eSPaolo Bonzini case PCI_POTAR: 282c0907c9eSPaolo Bonzini pci->pob[idx].potar = value; 283cb3778a0SAlexander Graf e500_update_pow(pci, idx); 284c0907c9eSPaolo Bonzini break; 285c0907c9eSPaolo Bonzini case PCI_POTEAR: 286c0907c9eSPaolo Bonzini pci->pob[idx].potear = value; 287cb3778a0SAlexander Graf e500_update_pow(pci, idx); 288c0907c9eSPaolo Bonzini break; 289c0907c9eSPaolo Bonzini case PCI_POWBAR: 290c0907c9eSPaolo Bonzini pci->pob[idx].powbar = value; 291cb3778a0SAlexander Graf e500_update_pow(pci, idx); 292c0907c9eSPaolo Bonzini break; 293c0907c9eSPaolo Bonzini case PCI_POWAR: 294c0907c9eSPaolo Bonzini pci->pob[idx].powar = value; 295cb3778a0SAlexander Graf e500_update_pow(pci, idx); 296c0907c9eSPaolo Bonzini break; 297c0907c9eSPaolo Bonzini default: 298c0907c9eSPaolo Bonzini break; 299c0907c9eSPaolo Bonzini }; 300c0907c9eSPaolo Bonzini break; 301c0907c9eSPaolo Bonzini 302c0907c9eSPaolo Bonzini case PPCE500_PCI_IW3: 303c0907c9eSPaolo Bonzini case PPCE500_PCI_IW2: 304c0907c9eSPaolo Bonzini case PPCE500_PCI_IW1: 305c0907c9eSPaolo Bonzini idx = ((addr >> 5) & 0x3) - 1; 306cb3778a0SAlexander Graf switch (addr & 0x1F) { 307c0907c9eSPaolo Bonzini case PCI_PITAR: 308c0907c9eSPaolo Bonzini pci->pib[idx].pitar = value; 309cb3778a0SAlexander Graf e500_update_piw(pci, idx); 310c0907c9eSPaolo Bonzini break; 311c0907c9eSPaolo Bonzini case PCI_PIWBAR: 312c0907c9eSPaolo Bonzini pci->pib[idx].piwbar = value; 313cb3778a0SAlexander Graf e500_update_piw(pci, idx); 314c0907c9eSPaolo Bonzini break; 315c0907c9eSPaolo Bonzini case PCI_PIWBEAR: 316c0907c9eSPaolo Bonzini pci->pib[idx].piwbear = value; 317cb3778a0SAlexander Graf e500_update_piw(pci, idx); 318c0907c9eSPaolo Bonzini break; 319c0907c9eSPaolo Bonzini case PCI_PIWAR: 320c0907c9eSPaolo Bonzini pci->pib[idx].piwar = value; 321cb3778a0SAlexander Graf e500_update_piw(pci, idx); 322c0907c9eSPaolo Bonzini break; 323c0907c9eSPaolo Bonzini default: 324c0907c9eSPaolo Bonzini break; 325c0907c9eSPaolo Bonzini }; 326c0907c9eSPaolo Bonzini break; 327c0907c9eSPaolo Bonzini 328c0907c9eSPaolo Bonzini case PPCE500_PCI_GASKET_TIMR: 329c0907c9eSPaolo Bonzini pci->gasket_time = value; 330c0907c9eSPaolo Bonzini break; 331c0907c9eSPaolo Bonzini 332c0907c9eSPaolo Bonzini default: 333c0907c9eSPaolo Bonzini break; 334c0907c9eSPaolo Bonzini }; 335c0907c9eSPaolo Bonzini } 336c0907c9eSPaolo Bonzini 337c0907c9eSPaolo Bonzini static const MemoryRegionOps e500_pci_reg_ops = { 338c0907c9eSPaolo Bonzini .read = pci_reg_read4, 339c0907c9eSPaolo Bonzini .write = pci_reg_write4, 340c0907c9eSPaolo Bonzini .endianness = DEVICE_BIG_ENDIAN, 341c0907c9eSPaolo Bonzini }; 342c0907c9eSPaolo Bonzini 343d575a6ceSBharat Bhushan static int mpc85xx_pci_map_irq(PCIDevice *pci_dev, int pin) 344c0907c9eSPaolo Bonzini { 345*8d40def6SPhilippe Mathieu-Daudé int devno = PCI_SLOT(pci_dev->devfn); 346c0907c9eSPaolo Bonzini int ret; 347c0907c9eSPaolo Bonzini 348d575a6ceSBharat Bhushan ret = ppce500_pci_map_irq_slot(devno, pin); 349c0907c9eSPaolo Bonzini 350c0907c9eSPaolo Bonzini pci_debug("%s: devfn %x irq %d -> %d devno:%x\n", __func__, 351d575a6ceSBharat Bhushan pci_dev->devfn, pin, ret, devno); 352c0907c9eSPaolo Bonzini 353c0907c9eSPaolo Bonzini return ret; 354c0907c9eSPaolo Bonzini } 355c0907c9eSPaolo Bonzini 356d575a6ceSBharat Bhushan static void mpc85xx_pci_set_irq(void *opaque, int pin, int level) 357c0907c9eSPaolo Bonzini { 3583016dca0SBharat Bhushan PPCE500PCIState *s = opaque; 3593016dca0SBharat Bhushan qemu_irq *pic = s->irq; 360c0907c9eSPaolo Bonzini 361d575a6ceSBharat Bhushan pci_debug("%s: PCI irq %d, level:%d\n", __func__, pin , level); 362c0907c9eSPaolo Bonzini 363d575a6ceSBharat Bhushan qemu_set_irq(pic[pin], level); 364c0907c9eSPaolo Bonzini } 365c0907c9eSPaolo Bonzini 3663016dca0SBharat Bhushan static PCIINTxRoute e500_route_intx_pin_to_irq(void *opaque, int pin) 3673016dca0SBharat Bhushan { 3683016dca0SBharat Bhushan PCIINTxRoute route; 3693016dca0SBharat Bhushan PPCE500PCIState *s = opaque; 3703016dca0SBharat Bhushan 3713016dca0SBharat Bhushan route.mode = PCI_INTX_ENABLED; 3723016dca0SBharat Bhushan route.irq = s->irq_num[pin]; 3733016dca0SBharat Bhushan 3743016dca0SBharat Bhushan pci_debug("%s: PCI irq-pin = %d, irq_num= %d\n", __func__, pin, route.irq); 3753016dca0SBharat Bhushan return route; 3763016dca0SBharat Bhushan } 3773016dca0SBharat Bhushan 378c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_pci_outbound = { 379c0907c9eSPaolo Bonzini .name = "pci_outbound", 380c0907c9eSPaolo Bonzini .version_id = 0, 381c0907c9eSPaolo Bonzini .minimum_version_id = 0, 382c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 383c0907c9eSPaolo Bonzini VMSTATE_UINT32(potar, struct pci_outbound), 384c0907c9eSPaolo Bonzini VMSTATE_UINT32(potear, struct pci_outbound), 385c0907c9eSPaolo Bonzini VMSTATE_UINT32(powbar, struct pci_outbound), 386c0907c9eSPaolo Bonzini VMSTATE_UINT32(powar, struct pci_outbound), 387c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 388c0907c9eSPaolo Bonzini } 389c0907c9eSPaolo Bonzini }; 390c0907c9eSPaolo Bonzini 391c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_pci_inbound = { 392c0907c9eSPaolo Bonzini .name = "pci_inbound", 393c0907c9eSPaolo Bonzini .version_id = 0, 394c0907c9eSPaolo Bonzini .minimum_version_id = 0, 395c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 396c0907c9eSPaolo Bonzini VMSTATE_UINT32(pitar, struct pci_inbound), 397c0907c9eSPaolo Bonzini VMSTATE_UINT32(piwbar, struct pci_inbound), 398c0907c9eSPaolo Bonzini VMSTATE_UINT32(piwbear, struct pci_inbound), 399c0907c9eSPaolo Bonzini VMSTATE_UINT32(piwar, struct pci_inbound), 400c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 401c0907c9eSPaolo Bonzini } 402c0907c9eSPaolo Bonzini }; 403c0907c9eSPaolo Bonzini 404c0907c9eSPaolo Bonzini static const VMStateDescription vmstate_ppce500_pci = { 405c0907c9eSPaolo Bonzini .name = "ppce500_pci", 406c0907c9eSPaolo Bonzini .version_id = 1, 407c0907c9eSPaolo Bonzini .minimum_version_id = 1, 408c0907c9eSPaolo Bonzini .fields = (VMStateField[]) { 409c0907c9eSPaolo Bonzini VMSTATE_STRUCT_ARRAY(pob, PPCE500PCIState, PPCE500_PCI_NR_POBS, 1, 410c0907c9eSPaolo Bonzini vmstate_pci_outbound, struct pci_outbound), 411c0907c9eSPaolo Bonzini VMSTATE_STRUCT_ARRAY(pib, PPCE500PCIState, PPCE500_PCI_NR_PIBS, 1, 412f2e2bc9cSPeter Maydell vmstate_pci_inbound, struct pci_inbound), 413c0907c9eSPaolo Bonzini VMSTATE_UINT32(gasket_time, PPCE500PCIState), 414c0907c9eSPaolo Bonzini VMSTATE_END_OF_LIST() 415c0907c9eSPaolo Bonzini } 416c0907c9eSPaolo Bonzini }; 417c0907c9eSPaolo Bonzini 418c0907c9eSPaolo Bonzini #include "exec/address-spaces.h" 419c0907c9eSPaolo Bonzini 4209af21dbeSMarkus Armbruster static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) 421c0907c9eSPaolo Bonzini { 422c0907c9eSPaolo Bonzini PPCE500PCIBridgeState *b = PPC_E500_PCI_BRIDGE(d); 423c0907c9eSPaolo Bonzini PPCE500CCSRState *ccsr = CCSR(container_get(qdev_get_machine(), 424c0907c9eSPaolo Bonzini "/e500-ccsr")); 425c0907c9eSPaolo Bonzini 42640c5dce9SPaolo Bonzini memory_region_init_alias(&b->bar0, OBJECT(ccsr), "e500-pci-bar0", &ccsr->ccsr_space, 427c0907c9eSPaolo Bonzini 0, int128_get64(ccsr->ccsr_space.size)); 428c0907c9eSPaolo Bonzini pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &b->bar0); 429c0907c9eSPaolo Bonzini } 430c0907c9eSPaolo Bonzini 431cb3778a0SAlexander Graf static AddressSpace *e500_pcihost_set_iommu(PCIBus *bus, void *opaque, 432cb3778a0SAlexander Graf int devfn) 433cb3778a0SAlexander Graf { 434cb3778a0SAlexander Graf PPCE500PCIState *s = opaque; 435cb3778a0SAlexander Graf 436cb3778a0SAlexander Graf return &s->bm_as; 437cb3778a0SAlexander Graf } 438cb3778a0SAlexander Graf 43973785b32SCédric Le Goater static void e500_pcihost_realize(DeviceState *dev, Error **errp) 440c0907c9eSPaolo Bonzini { 44173785b32SCédric Le Goater SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 442c0907c9eSPaolo Bonzini PCIHostState *h; 443c0907c9eSPaolo Bonzini PPCE500PCIState *s; 444c0907c9eSPaolo Bonzini PCIBus *b; 445c0907c9eSPaolo Bonzini int i; 446c0907c9eSPaolo Bonzini 447c0907c9eSPaolo Bonzini h = PCI_HOST_BRIDGE(dev); 448c0907c9eSPaolo Bonzini s = PPC_E500_PCI_HOST_BRIDGE(dev); 449c0907c9eSPaolo Bonzini 450c0907c9eSPaolo Bonzini for (i = 0; i < ARRAY_SIZE(s->irq); i++) { 45173785b32SCédric Le Goater sysbus_init_irq(sbd, &s->irq[i]); 452c0907c9eSPaolo Bonzini } 453c0907c9eSPaolo Bonzini 4543016dca0SBharat Bhushan for (i = 0; i < PCI_NUM_PINS; i++) { 4553016dca0SBharat Bhushan s->irq_num[i] = s->first_pin_irq + i; 4563016dca0SBharat Bhushan } 4573016dca0SBharat Bhushan 45840c5dce9SPaolo Bonzini memory_region_init(&s->pio, OBJECT(s), "pci-pio", PCIE500_PCI_IOLEN); 459cb3778a0SAlexander Graf memory_region_init(&s->busmem, OBJECT(s), "pci bus memory", UINT64_MAX); 460cb3778a0SAlexander Graf 461cb3778a0SAlexander Graf /* PIO lives at the bottom of our bus space */ 462cb3778a0SAlexander Graf memory_region_add_subregion_overlap(&s->busmem, 0, &s->pio, -2); 463c0907c9eSPaolo Bonzini 46473785b32SCédric Le Goater b = pci_register_root_bus(dev, NULL, mpc85xx_pci_set_irq, 465cb3778a0SAlexander Graf mpc85xx_pci_map_irq, s, &s->busmem, &s->pio, 466cb3778a0SAlexander Graf PCI_DEVFN(s->first_slot, 0), 4, TYPE_PCI_BUS); 467c0907c9eSPaolo Bonzini h->bus = b; 468c0907c9eSPaolo Bonzini 469cb3778a0SAlexander Graf /* Set up PCI view of memory */ 470cb3778a0SAlexander Graf memory_region_init(&s->bm, OBJECT(s), "bm-e500", UINT64_MAX); 471cb3778a0SAlexander Graf memory_region_add_subregion(&s->bm, 0x0, &s->busmem); 472cb3778a0SAlexander Graf address_space_init(&s->bm_as, &s->bm, "pci-bm"); 473cb3778a0SAlexander Graf pci_setup_iommu(b, e500_pcihost_set_iommu, s); 474cb3778a0SAlexander Graf 475c0907c9eSPaolo Bonzini pci_create_simple(b, 0, "e500-host-bridge"); 476c0907c9eSPaolo Bonzini 47740c5dce9SPaolo Bonzini memory_region_init(&s->container, OBJECT(h), "pci-container", PCIE500_ALL_SIZE); 47840c5dce9SPaolo Bonzini memory_region_init_io(&h->conf_mem, OBJECT(h), &pci_host_conf_be_ops, h, 479c0907c9eSPaolo Bonzini "pci-conf-idx", 4); 48040c5dce9SPaolo Bonzini memory_region_init_io(&h->data_mem, OBJECT(h), &pci_host_data_le_ops, h, 481c0907c9eSPaolo Bonzini "pci-conf-data", 4); 48240c5dce9SPaolo Bonzini memory_region_init_io(&s->iomem, OBJECT(s), &e500_pci_reg_ops, s, 483c0907c9eSPaolo Bonzini "pci.reg", PCIE500_REG_SIZE); 484c0907c9eSPaolo Bonzini memory_region_add_subregion(&s->container, PCIE500_CFGADDR, &h->conf_mem); 485c0907c9eSPaolo Bonzini memory_region_add_subregion(&s->container, PCIE500_CFGDATA, &h->data_mem); 486c0907c9eSPaolo Bonzini memory_region_add_subregion(&s->container, PCIE500_REG_BASE, &s->iomem); 48773785b32SCédric Le Goater sysbus_init_mmio(sbd, &s->container); 4883016dca0SBharat Bhushan pci_bus_set_route_irq_fn(b, e500_route_intx_pin_to_irq); 489c0907c9eSPaolo Bonzini } 490c0907c9eSPaolo Bonzini 491c0907c9eSPaolo Bonzini static void e500_host_bridge_class_init(ObjectClass *klass, void *data) 492c0907c9eSPaolo Bonzini { 493c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 494c0907c9eSPaolo Bonzini PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 495c0907c9eSPaolo Bonzini 4969af21dbeSMarkus Armbruster k->realize = e500_pcihost_bridge_realize; 497c0907c9eSPaolo Bonzini k->vendor_id = PCI_VENDOR_ID_FREESCALE; 498c0907c9eSPaolo Bonzini k->device_id = PCI_DEVICE_ID_MPC8533E; 499c0907c9eSPaolo Bonzini k->class_id = PCI_CLASS_PROCESSOR_POWERPC; 500c0907c9eSPaolo Bonzini dc->desc = "Host bridge"; 50108c58f92SMarkus Armbruster /* 50208c58f92SMarkus Armbruster * PCI-facing part of the host bridge, not usable without the 50308c58f92SMarkus Armbruster * host-facing part, which can't be device_add'ed, yet. 50408c58f92SMarkus Armbruster */ 505e90f2a8cSEduardo Habkost dc->user_creatable = false; 506c0907c9eSPaolo Bonzini } 507c0907c9eSPaolo Bonzini 508c0907c9eSPaolo Bonzini static const TypeInfo e500_host_bridge_info = { 5098c2eedceSEduardo Habkost .name = TYPE_PPC_E500_PCI_BRIDGE, 510c0907c9eSPaolo Bonzini .parent = TYPE_PCI_DEVICE, 511c0907c9eSPaolo Bonzini .instance_size = sizeof(PPCE500PCIBridgeState), 512c0907c9eSPaolo Bonzini .class_init = e500_host_bridge_class_init, 513fd3b02c8SEduardo Habkost .interfaces = (InterfaceInfo[]) { 514fd3b02c8SEduardo Habkost { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 515fd3b02c8SEduardo Habkost { }, 516fd3b02c8SEduardo Habkost }, 517c0907c9eSPaolo Bonzini }; 518c0907c9eSPaolo Bonzini 519c0907c9eSPaolo Bonzini static Property pcihost_properties[] = { 520c0907c9eSPaolo Bonzini DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), 5213016dca0SBharat Bhushan DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1), 522c0907c9eSPaolo Bonzini DEFINE_PROP_END_OF_LIST(), 523c0907c9eSPaolo Bonzini }; 524c0907c9eSPaolo Bonzini 525c0907c9eSPaolo Bonzini static void e500_pcihost_class_init(ObjectClass *klass, void *data) 526c0907c9eSPaolo Bonzini { 527c0907c9eSPaolo Bonzini DeviceClass *dc = DEVICE_CLASS(klass); 528c0907c9eSPaolo Bonzini 52973785b32SCédric Le Goater dc->realize = e500_pcihost_realize; 530125ee0edSMarcel Apfelbaum set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 5314f67d30bSMarc-André Lureau device_class_set_props(dc, pcihost_properties); 532c0907c9eSPaolo Bonzini dc->vmsd = &vmstate_ppce500_pci; 533c0907c9eSPaolo Bonzini } 534c0907c9eSPaolo Bonzini 535c0907c9eSPaolo Bonzini static const TypeInfo e500_pcihost_info = { 536c0907c9eSPaolo Bonzini .name = TYPE_PPC_E500_PCI_HOST_BRIDGE, 537c0907c9eSPaolo Bonzini .parent = TYPE_PCI_HOST_BRIDGE, 538c0907c9eSPaolo Bonzini .instance_size = sizeof(PPCE500PCIState), 539c0907c9eSPaolo Bonzini .class_init = e500_pcihost_class_init, 540c0907c9eSPaolo Bonzini }; 541c0907c9eSPaolo Bonzini 542c0907c9eSPaolo Bonzini static void e500_pci_register_types(void) 543c0907c9eSPaolo Bonzini { 544c0907c9eSPaolo Bonzini type_register_static(&e500_pcihost_info); 545c0907c9eSPaolo Bonzini type_register_static(&e500_host_bridge_info); 546c0907c9eSPaolo Bonzini } 547c0907c9eSPaolo Bonzini 548c0907c9eSPaolo Bonzini type_init(e500_pci_register_types) 549