1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "qapi/error.h" 11 #include "qemu-common.h" 12 #include "qemu/log.h" 13 #include "target/ppc/cpu.h" 14 #include "hw/ppc/fdt.h" 15 #include "hw/pci-host/pnv_phb4_regs.h" 16 #include "hw/pci-host/pnv_phb4.h" 17 #include "hw/ppc/pnv_xscom.h" 18 #include "hw/pci/pci_bridge.h" 19 #include "hw/pci/pci_bus.h" 20 #include "hw/ppc/pnv.h" 21 #include "hw/qdev-properties.h" 22 #include "sysemu/sysemu.h" 23 24 #include <libfdt.h> 25 26 #define phb_pec_error(pec, fmt, ...) \ 27 qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ 28 (pec)->chip_id, (pec)->index, ## __VA_ARGS__) 29 30 31 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr, 32 unsigned size) 33 { 34 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 35 uint32_t reg = addr >> 3; 36 37 /* TODO: add list of allowed registers and error out if not */ 38 return pec->nest_regs[reg]; 39 } 40 41 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr, 42 uint64_t val, unsigned size) 43 { 44 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 45 uint32_t reg = addr >> 3; 46 47 switch (reg) { 48 case PEC_NEST_PBCQ_HW_CONFIG: 49 case PEC_NEST_DROP_PRIO_CTRL: 50 case PEC_NEST_PBCQ_ERR_INJECT: 51 case PEC_NEST_PCI_NEST_CLK_TRACE_CTL: 52 case PEC_NEST_PBCQ_PMON_CTRL: 53 case PEC_NEST_PBCQ_PBUS_ADDR_EXT: 54 case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT: 55 case PEC_NEST_CAPP_CTRL: 56 case PEC_NEST_PBCQ_READ_STK_OVR: 57 case PEC_NEST_PBCQ_WRITE_STK_OVR: 58 case PEC_NEST_PBCQ_STORE_STK_OVR: 59 case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL: 60 pec->nest_regs[reg] = val; 61 break; 62 default: 63 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 64 addr, val); 65 } 66 } 67 68 static const MemoryRegionOps pnv_pec_nest_xscom_ops = { 69 .read = pnv_pec_nest_xscom_read, 70 .write = pnv_pec_nest_xscom_write, 71 .valid.min_access_size = 8, 72 .valid.max_access_size = 8, 73 .impl.min_access_size = 8, 74 .impl.max_access_size = 8, 75 .endianness = DEVICE_BIG_ENDIAN, 76 }; 77 78 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr, 79 unsigned size) 80 { 81 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 82 uint32_t reg = addr >> 3; 83 84 /* TODO: add list of allowed registers and error out if not */ 85 return pec->pci_regs[reg]; 86 } 87 88 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr, 89 uint64_t val, unsigned size) 90 { 91 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 92 uint32_t reg = addr >> 3; 93 94 switch (reg) { 95 case PEC_PCI_PBAIB_HW_CONFIG: 96 case PEC_PCI_PBAIB_READ_STK_OVR: 97 pec->pci_regs[reg] = val; 98 break; 99 default: 100 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 101 addr, val); 102 } 103 } 104 105 static const MemoryRegionOps pnv_pec_pci_xscom_ops = { 106 .read = pnv_pec_pci_xscom_read, 107 .write = pnv_pec_pci_xscom_write, 108 .valid.min_access_size = 8, 109 .valid.max_access_size = 8, 110 .impl.min_access_size = 8, 111 .impl.max_access_size = 8, 112 .endianness = DEVICE_BIG_ENDIAN, 113 }; 114 115 static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, 116 int stack_no, 117 Error **errp) 118 { 119 PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); 120 int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); 121 122 object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), 123 &error_abort); 124 object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id, 125 &error_fatal); 126 object_property_set_int(OBJECT(phb), "index", phb_id, 127 &error_fatal); 128 129 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 130 return; 131 } 132 133 /* Add a single Root port if running with defaults */ 134 pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), 135 PNV_PHB4_PEC_GET_CLASS(pec)->rp_model); 136 137 } 138 139 static void pnv_pec_realize(DeviceState *dev, Error **errp) 140 { 141 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 142 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 143 char name[64]; 144 int i; 145 146 if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { 147 error_setg(errp, "invalid PEC index: %d", pec->index); 148 return; 149 } 150 151 pec->num_phbs = pecc->num_phbs[pec->index]; 152 153 /* Create PHBs if running with defaults */ 154 if (defaults_enabled()) { 155 for (i = 0; i < pec->num_phbs; i++) { 156 pnv_pec_default_phb_realize(pec, i, errp); 157 } 158 } 159 160 /* Initialize the XSCOM regions for the PEC registers */ 161 snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id, 162 pec->index); 163 pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev), 164 &pnv_pec_nest_xscom_ops, pec, name, 165 PHB4_PEC_NEST_REGS_COUNT); 166 167 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id, 168 pec->index); 169 pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev), 170 &pnv_pec_pci_xscom_ops, pec, name, 171 PHB4_PEC_PCI_REGS_COUNT); 172 } 173 174 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, 175 int xscom_offset) 176 { 177 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 178 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev); 179 uint32_t nbase = pecc->xscom_nest_base(pec); 180 uint32_t pbase = pecc->xscom_pci_base(pec); 181 int offset, i; 182 char *name; 183 uint32_t reg[] = { 184 cpu_to_be32(nbase), 185 cpu_to_be32(pecc->xscom_nest_size), 186 cpu_to_be32(pbase), 187 cpu_to_be32(pecc->xscom_pci_size), 188 }; 189 190 name = g_strdup_printf("pbcq@%x", nbase); 191 offset = fdt_add_subnode(fdt, xscom_offset, name); 192 _FDT(offset); 193 g_free(name); 194 195 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 196 197 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index))); 198 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1))); 199 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0))); 200 _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat, 201 pecc->compat_size))); 202 203 for (i = 0; i < pec->num_phbs; i++) { 204 int phb_id = pnv_phb4_pec_get_phb_id(pec, i); 205 int stk_offset; 206 207 name = g_strdup_printf("stack@%x", i); 208 stk_offset = fdt_add_subnode(fdt, offset, name); 209 _FDT(stk_offset); 210 g_free(name); 211 _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat, 212 pecc->stk_compat_size))); 213 _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i))); 214 _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id))); 215 } 216 217 return 0; 218 } 219 220 static Property pnv_pec_properties[] = { 221 DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), 222 DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), 223 DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, 224 PnvChip *), 225 DEFINE_PROP_END_OF_LIST(), 226 }; 227 228 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec) 229 { 230 return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index; 231 } 232 233 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) 234 { 235 return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; 236 } 237 238 /* 239 * PEC0 -> 1 phb 240 * PEC1 -> 2 phb 241 * PEC2 -> 3 phbs 242 */ 243 static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 }; 244 245 static void pnv_pec_class_init(ObjectClass *klass, void *data) 246 { 247 DeviceClass *dc = DEVICE_CLASS(klass); 248 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 249 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass); 250 static const char compat[] = "ibm,power9-pbcq"; 251 static const char stk_compat[] = "ibm,power9-phb-stack"; 252 253 xdc->dt_xscom = pnv_pec_dt_xscom; 254 255 dc->realize = pnv_pec_realize; 256 device_class_set_props(dc, pnv_pec_properties); 257 dc->user_creatable = false; 258 259 pecc->xscom_nest_base = pnv_pec_xscom_nest_base; 260 pecc->xscom_pci_base = pnv_pec_xscom_pci_base; 261 pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE; 262 pecc->xscom_pci_size = PNV9_XSCOM_PEC_PCI_SIZE; 263 pecc->compat = compat; 264 pecc->compat_size = sizeof(compat); 265 pecc->stk_compat = stk_compat; 266 pecc->stk_compat_size = sizeof(stk_compat); 267 pecc->version = PNV_PHB4_VERSION; 268 pecc->num_phbs = pnv_pec_num_phbs; 269 pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT; 270 } 271 272 static const TypeInfo pnv_pec_type_info = { 273 .name = TYPE_PNV_PHB4_PEC, 274 .parent = TYPE_DEVICE, 275 .instance_size = sizeof(PnvPhb4PecState), 276 .class_init = pnv_pec_class_init, 277 .class_size = sizeof(PnvPhb4PecClass), 278 .interfaces = (InterfaceInfo[]) { 279 { TYPE_PNV_XSCOM_INTERFACE }, 280 { } 281 } 282 }; 283 284 static void pnv_pec_register_types(void) 285 { 286 type_register_static(&pnv_pec_type_info); 287 } 288 289 type_init(pnv_pec_register_types); 290