1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "qapi/error.h" 11 #include "qemu-common.h" 12 #include "qemu/log.h" 13 #include "target/ppc/cpu.h" 14 #include "hw/ppc/fdt.h" 15 #include "hw/pci-host/pnv_phb4_regs.h" 16 #include "hw/pci-host/pnv_phb4.h" 17 #include "hw/ppc/pnv_xscom.h" 18 #include "hw/pci/pci_bridge.h" 19 #include "hw/pci/pci_bus.h" 20 #include "hw/ppc/pnv.h" 21 #include "hw/qdev-properties.h" 22 23 #include <libfdt.h> 24 25 #define phb_pec_error(pec, fmt, ...) \ 26 qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ 27 (pec)->chip_id, (pec)->index, ## __VA_ARGS__) 28 29 30 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr, 31 unsigned size) 32 { 33 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 34 uint32_t reg = addr >> 3; 35 36 /* TODO: add list of allowed registers and error out if not */ 37 return pec->nest_regs[reg]; 38 } 39 40 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr, 41 uint64_t val, unsigned size) 42 { 43 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 44 uint32_t reg = addr >> 3; 45 46 switch (reg) { 47 case PEC_NEST_PBCQ_HW_CONFIG: 48 case PEC_NEST_DROP_PRIO_CTRL: 49 case PEC_NEST_PBCQ_ERR_INJECT: 50 case PEC_NEST_PCI_NEST_CLK_TRACE_CTL: 51 case PEC_NEST_PBCQ_PMON_CTRL: 52 case PEC_NEST_PBCQ_PBUS_ADDR_EXT: 53 case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT: 54 case PEC_NEST_CAPP_CTRL: 55 case PEC_NEST_PBCQ_READ_STK_OVR: 56 case PEC_NEST_PBCQ_WRITE_STK_OVR: 57 case PEC_NEST_PBCQ_STORE_STK_OVR: 58 case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL: 59 pec->nest_regs[reg] = val; 60 break; 61 default: 62 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 63 addr, val); 64 } 65 } 66 67 static const MemoryRegionOps pnv_pec_nest_xscom_ops = { 68 .read = pnv_pec_nest_xscom_read, 69 .write = pnv_pec_nest_xscom_write, 70 .valid.min_access_size = 8, 71 .valid.max_access_size = 8, 72 .impl.min_access_size = 8, 73 .impl.max_access_size = 8, 74 .endianness = DEVICE_BIG_ENDIAN, 75 }; 76 77 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr, 78 unsigned size) 79 { 80 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 81 uint32_t reg = addr >> 3; 82 83 /* TODO: add list of allowed registers and error out if not */ 84 return pec->pci_regs[reg]; 85 } 86 87 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr, 88 uint64_t val, unsigned size) 89 { 90 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 91 uint32_t reg = addr >> 3; 92 93 switch (reg) { 94 case PEC_PCI_PBAIB_HW_CONFIG: 95 case PEC_PCI_PBAIB_READ_STK_OVR: 96 pec->pci_regs[reg] = val; 97 break; 98 default: 99 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 100 addr, val); 101 } 102 } 103 104 static const MemoryRegionOps pnv_pec_pci_xscom_ops = { 105 .read = pnv_pec_pci_xscom_read, 106 .write = pnv_pec_pci_xscom_write, 107 .valid.min_access_size = 8, 108 .valid.max_access_size = 8, 109 .impl.min_access_size = 8, 110 .impl.max_access_size = 8, 111 .endianness = DEVICE_BIG_ENDIAN, 112 }; 113 114 static void pnv_pec_instance_init(Object *obj) 115 { 116 PnvPhb4PecState *pec = PNV_PHB4_PEC(obj); 117 int i; 118 119 for (i = 0; i < PHB4_PEC_MAX_STACKS; i++) { 120 object_initialize_child(obj, "stack[*]", &pec->stacks[i], 121 TYPE_PNV_PHB4_PEC_STACK); 122 } 123 } 124 125 static void pnv_pec_realize(DeviceState *dev, Error **errp) 126 { 127 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 128 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 129 char name[64]; 130 int i; 131 132 if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { 133 error_setg(errp, "invalid PEC index: %d", pec->index); 134 return; 135 } 136 137 pec->num_stacks = pecc->num_stacks[pec->index]; 138 139 /* Create stacks */ 140 for (i = 0; i < pec->num_stacks; i++) { 141 PnvPhb4PecStack *stack = &pec->stacks[i]; 142 Object *stk_obj = OBJECT(stack); 143 144 object_property_set_int(stk_obj, "stack-no", i, &error_abort); 145 object_property_set_link(stk_obj, "pec", OBJECT(pec), &error_abort); 146 if (!qdev_realize(DEVICE(stk_obj), NULL, errp)) { 147 return; 148 } 149 } 150 for (; i < PHB4_PEC_MAX_STACKS; i++) { 151 object_unparent(OBJECT(&pec->stacks[i])); 152 } 153 154 /* Initialize the XSCOM regions for the PEC registers */ 155 snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id, 156 pec->index); 157 pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev), 158 &pnv_pec_nest_xscom_ops, pec, name, 159 PHB4_PEC_NEST_REGS_COUNT); 160 161 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id, 162 pec->index); 163 pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev), 164 &pnv_pec_pci_xscom_ops, pec, name, 165 PHB4_PEC_PCI_REGS_COUNT); 166 } 167 168 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, 169 int xscom_offset) 170 { 171 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 172 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev); 173 uint32_t nbase = pecc->xscom_nest_base(pec); 174 uint32_t pbase = pecc->xscom_pci_base(pec); 175 int offset, i; 176 char *name; 177 uint32_t reg[] = { 178 cpu_to_be32(nbase), 179 cpu_to_be32(pecc->xscom_nest_size), 180 cpu_to_be32(pbase), 181 cpu_to_be32(pecc->xscom_pci_size), 182 }; 183 184 name = g_strdup_printf("pbcq@%x", nbase); 185 offset = fdt_add_subnode(fdt, xscom_offset, name); 186 _FDT(offset); 187 g_free(name); 188 189 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 190 191 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index))); 192 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1))); 193 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0))); 194 _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat, 195 pecc->compat_size))); 196 197 for (i = 0; i < pec->num_stacks; i++) { 198 int phb_id = pnv_phb4_pec_get_phb_id(pec, i); 199 int stk_offset; 200 201 name = g_strdup_printf("stack@%x", i); 202 stk_offset = fdt_add_subnode(fdt, offset, name); 203 _FDT(stk_offset); 204 g_free(name); 205 _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat, 206 pecc->stk_compat_size))); 207 _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i))); 208 _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id))); 209 } 210 211 return 0; 212 } 213 214 static Property pnv_pec_properties[] = { 215 DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), 216 DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), 217 DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, 218 PnvChip *), 219 DEFINE_PROP_END_OF_LIST(), 220 }; 221 222 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec) 223 { 224 return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index; 225 } 226 227 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) 228 { 229 return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; 230 } 231 232 /* 233 * PEC0 -> 1 stack 234 * PEC1 -> 2 stacks 235 * PEC2 -> 3 stacks 236 */ 237 static const uint32_t pnv_pec_num_stacks[] = { 1, 2, 3 }; 238 239 static void pnv_pec_class_init(ObjectClass *klass, void *data) 240 { 241 DeviceClass *dc = DEVICE_CLASS(klass); 242 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 243 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass); 244 static const char compat[] = "ibm,power9-pbcq"; 245 static const char stk_compat[] = "ibm,power9-phb-stack"; 246 247 xdc->dt_xscom = pnv_pec_dt_xscom; 248 249 dc->realize = pnv_pec_realize; 250 device_class_set_props(dc, pnv_pec_properties); 251 dc->user_creatable = false; 252 253 pecc->xscom_nest_base = pnv_pec_xscom_nest_base; 254 pecc->xscom_pci_base = pnv_pec_xscom_pci_base; 255 pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE; 256 pecc->xscom_pci_size = PNV9_XSCOM_PEC_PCI_SIZE; 257 pecc->compat = compat; 258 pecc->compat_size = sizeof(compat); 259 pecc->stk_compat = stk_compat; 260 pecc->stk_compat_size = sizeof(stk_compat); 261 pecc->version = PNV_PHB4_VERSION; 262 pecc->num_stacks = pnv_pec_num_stacks; 263 } 264 265 static const TypeInfo pnv_pec_type_info = { 266 .name = TYPE_PNV_PHB4_PEC, 267 .parent = TYPE_DEVICE, 268 .instance_size = sizeof(PnvPhb4PecState), 269 .instance_init = pnv_pec_instance_init, 270 .class_init = pnv_pec_class_init, 271 .class_size = sizeof(PnvPhb4PecClass), 272 .interfaces = (InterfaceInfo[]) { 273 { TYPE_PNV_XSCOM_INTERFACE }, 274 { } 275 } 276 }; 277 278 static void pnv_pec_stk_instance_init(Object *obj) 279 { 280 PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(obj); 281 282 object_initialize_child(obj, "phb", &stack->phb, TYPE_PNV_PHB4); 283 } 284 285 static void pnv_pec_stk_realize(DeviceState *dev, Error **errp) 286 { 287 PnvPhb4PecStack *stack = PNV_PHB4_PEC_STACK(dev); 288 PnvPhb4PecState *pec = stack->pec; 289 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 290 int phb_id = pnv_phb4_pec_get_phb_id(pec, stack->stack_no); 291 292 object_property_set_int(OBJECT(&stack->phb), "chip-id", pec->chip_id, 293 &error_fatal); 294 object_property_set_int(OBJECT(&stack->phb), "index", phb_id, 295 &error_fatal); 296 object_property_set_int(OBJECT(&stack->phb), "version", pecc->version, 297 &error_fatal); 298 object_property_set_link(OBJECT(&stack->phb), "stack", OBJECT(stack), 299 &error_abort); 300 if (!sysbus_realize(SYS_BUS_DEVICE(&stack->phb), errp)) { 301 return; 302 } 303 } 304 305 static Property pnv_pec_stk_properties[] = { 306 DEFINE_PROP_UINT32("stack-no", PnvPhb4PecStack, stack_no, 0), 307 DEFINE_PROP_LINK("pec", PnvPhb4PecStack, pec, TYPE_PNV_PHB4_PEC, 308 PnvPhb4PecState *), 309 DEFINE_PROP_END_OF_LIST(), 310 }; 311 312 static void pnv_pec_stk_class_init(ObjectClass *klass, void *data) 313 { 314 DeviceClass *dc = DEVICE_CLASS(klass); 315 316 device_class_set_props(dc, pnv_pec_stk_properties); 317 dc->realize = pnv_pec_stk_realize; 318 dc->user_creatable = false; 319 320 /* TODO: reset regs ? */ 321 } 322 323 static const TypeInfo pnv_pec_stk_type_info = { 324 .name = TYPE_PNV_PHB4_PEC_STACK, 325 .parent = TYPE_DEVICE, 326 .instance_size = sizeof(PnvPhb4PecStack), 327 .instance_init = pnv_pec_stk_instance_init, 328 .class_init = pnv_pec_stk_class_init, 329 .interfaces = (InterfaceInfo[]) { 330 { TYPE_PNV_XSCOM_INTERFACE }, 331 { } 332 } 333 }; 334 335 static void pnv_pec_register_types(void) 336 { 337 type_register_static(&pnv_pec_type_info); 338 type_register_static(&pnv_pec_stk_type_info); 339 } 340 341 type_init(pnv_pec_register_types); 342