1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "qapi/error.h" 11 #include "qemu-common.h" 12 #include "qemu/log.h" 13 #include "target/ppc/cpu.h" 14 #include "hw/ppc/fdt.h" 15 #include "hw/pci-host/pnv_phb4_regs.h" 16 #include "hw/pci-host/pnv_phb4.h" 17 #include "hw/ppc/pnv_xscom.h" 18 #include "hw/pci/pci_bridge.h" 19 #include "hw/pci/pci_bus.h" 20 #include "hw/ppc/pnv.h" 21 #include "hw/qdev-properties.h" 22 #include "sysemu/sysemu.h" 23 24 #include <libfdt.h> 25 26 #define phb_pec_error(pec, fmt, ...) \ 27 qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ 28 (pec)->chip_id, (pec)->index, ## __VA_ARGS__) 29 30 31 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr, 32 unsigned size) 33 { 34 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 35 uint32_t reg = addr >> 3; 36 37 /* TODO: add list of allowed registers and error out if not */ 38 return pec->nest_regs[reg]; 39 } 40 41 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr, 42 uint64_t val, unsigned size) 43 { 44 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 45 uint32_t reg = addr >> 3; 46 47 switch (reg) { 48 case PEC_NEST_PBCQ_HW_CONFIG: 49 case PEC_NEST_DROP_PRIO_CTRL: 50 case PEC_NEST_PBCQ_ERR_INJECT: 51 case PEC_NEST_PCI_NEST_CLK_TRACE_CTL: 52 case PEC_NEST_PBCQ_PMON_CTRL: 53 case PEC_NEST_PBCQ_PBUS_ADDR_EXT: 54 case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT: 55 case PEC_NEST_CAPP_CTRL: 56 case PEC_NEST_PBCQ_READ_STK_OVR: 57 case PEC_NEST_PBCQ_WRITE_STK_OVR: 58 case PEC_NEST_PBCQ_STORE_STK_OVR: 59 case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL: 60 pec->nest_regs[reg] = val; 61 break; 62 default: 63 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 64 addr, val); 65 } 66 } 67 68 static const MemoryRegionOps pnv_pec_nest_xscom_ops = { 69 .read = pnv_pec_nest_xscom_read, 70 .write = pnv_pec_nest_xscom_write, 71 .valid.min_access_size = 8, 72 .valid.max_access_size = 8, 73 .impl.min_access_size = 8, 74 .impl.max_access_size = 8, 75 .endianness = DEVICE_BIG_ENDIAN, 76 }; 77 78 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr, 79 unsigned size) 80 { 81 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 82 uint32_t reg = addr >> 3; 83 84 /* TODO: add list of allowed registers and error out if not */ 85 return pec->pci_regs[reg]; 86 } 87 88 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr, 89 uint64_t val, unsigned size) 90 { 91 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 92 uint32_t reg = addr >> 3; 93 94 switch (reg) { 95 case PEC_PCI_PBAIB_HW_CONFIG: 96 case PEC_PCI_PBAIB_READ_STK_OVR: 97 pec->pci_regs[reg] = val; 98 break; 99 default: 100 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 101 addr, val); 102 } 103 } 104 105 static const MemoryRegionOps pnv_pec_pci_xscom_ops = { 106 .read = pnv_pec_pci_xscom_read, 107 .write = pnv_pec_pci_xscom_write, 108 .valid.min_access_size = 8, 109 .valid.max_access_size = 8, 110 .impl.min_access_size = 8, 111 .impl.max_access_size = 8, 112 .endianness = DEVICE_BIG_ENDIAN, 113 }; 114 115 static void pnv_pec_default_phb_realize(PnvPhb4PecState *pec, 116 int stack_no, 117 Error **errp) 118 { 119 PnvPHB4 *phb = PNV_PHB4(qdev_new(TYPE_PNV_PHB4)); 120 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 121 int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); 122 123 object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), 124 &error_abort); 125 object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id, 126 &error_fatal); 127 object_property_set_int(OBJECT(phb), "index", phb_id, 128 &error_fatal); 129 object_property_set_int(OBJECT(phb), "version", pecc->version, 130 &error_fatal); 131 132 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 133 return; 134 } 135 136 /* Add a single Root port if running with defaults */ 137 pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), 138 PNV_PHB4_PEC_GET_CLASS(pec)->rp_model); 139 140 } 141 142 static void pnv_pec_realize(DeviceState *dev, Error **errp) 143 { 144 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 145 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 146 char name[64]; 147 int i; 148 149 if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { 150 error_setg(errp, "invalid PEC index: %d", pec->index); 151 return; 152 } 153 154 pec->num_phbs = pecc->num_phbs[pec->index]; 155 156 /* Create PHBs if running with defaults */ 157 if (defaults_enabled()) { 158 for (i = 0; i < pec->num_phbs; i++) { 159 pnv_pec_default_phb_realize(pec, i, errp); 160 } 161 } 162 163 /* Initialize the XSCOM regions for the PEC registers */ 164 snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id, 165 pec->index); 166 pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev), 167 &pnv_pec_nest_xscom_ops, pec, name, 168 PHB4_PEC_NEST_REGS_COUNT); 169 170 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id, 171 pec->index); 172 pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev), 173 &pnv_pec_pci_xscom_ops, pec, name, 174 PHB4_PEC_PCI_REGS_COUNT); 175 } 176 177 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, 178 int xscom_offset) 179 { 180 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 181 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev); 182 uint32_t nbase = pecc->xscom_nest_base(pec); 183 uint32_t pbase = pecc->xscom_pci_base(pec); 184 int offset, i; 185 char *name; 186 uint32_t reg[] = { 187 cpu_to_be32(nbase), 188 cpu_to_be32(pecc->xscom_nest_size), 189 cpu_to_be32(pbase), 190 cpu_to_be32(pecc->xscom_pci_size), 191 }; 192 193 name = g_strdup_printf("pbcq@%x", nbase); 194 offset = fdt_add_subnode(fdt, xscom_offset, name); 195 _FDT(offset); 196 g_free(name); 197 198 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 199 200 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index))); 201 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1))); 202 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0))); 203 _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat, 204 pecc->compat_size))); 205 206 for (i = 0; i < pec->num_phbs; i++) { 207 int phb_id = pnv_phb4_pec_get_phb_id(pec, i); 208 int stk_offset; 209 210 name = g_strdup_printf("stack@%x", i); 211 stk_offset = fdt_add_subnode(fdt, offset, name); 212 _FDT(stk_offset); 213 g_free(name); 214 _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat, 215 pecc->stk_compat_size))); 216 _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i))); 217 _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", phb_id))); 218 } 219 220 return 0; 221 } 222 223 static Property pnv_pec_properties[] = { 224 DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), 225 DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), 226 DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, 227 PnvChip *), 228 DEFINE_PROP_END_OF_LIST(), 229 }; 230 231 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec) 232 { 233 return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index; 234 } 235 236 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) 237 { 238 return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; 239 } 240 241 /* 242 * PEC0 -> 1 phb 243 * PEC1 -> 2 phb 244 * PEC2 -> 3 phbs 245 */ 246 static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 }; 247 248 static void pnv_pec_class_init(ObjectClass *klass, void *data) 249 { 250 DeviceClass *dc = DEVICE_CLASS(klass); 251 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 252 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass); 253 static const char compat[] = "ibm,power9-pbcq"; 254 static const char stk_compat[] = "ibm,power9-phb-stack"; 255 256 xdc->dt_xscom = pnv_pec_dt_xscom; 257 258 dc->realize = pnv_pec_realize; 259 device_class_set_props(dc, pnv_pec_properties); 260 dc->user_creatable = false; 261 262 pecc->xscom_nest_base = pnv_pec_xscom_nest_base; 263 pecc->xscom_pci_base = pnv_pec_xscom_pci_base; 264 pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE; 265 pecc->xscom_pci_size = PNV9_XSCOM_PEC_PCI_SIZE; 266 pecc->compat = compat; 267 pecc->compat_size = sizeof(compat); 268 pecc->stk_compat = stk_compat; 269 pecc->stk_compat_size = sizeof(stk_compat); 270 pecc->version = PNV_PHB4_VERSION; 271 pecc->num_phbs = pnv_pec_num_phbs; 272 pecc->rp_model = TYPE_PNV_PHB4_ROOT_PORT; 273 } 274 275 static const TypeInfo pnv_pec_type_info = { 276 .name = TYPE_PNV_PHB4_PEC, 277 .parent = TYPE_DEVICE, 278 .instance_size = sizeof(PnvPhb4PecState), 279 .class_init = pnv_pec_class_init, 280 .class_size = sizeof(PnvPhb4PecClass), 281 .interfaces = (InterfaceInfo[]) { 282 { TYPE_PNV_XSCOM_INTERFACE }, 283 { } 284 } 285 }; 286 287 static void pnv_pec_register_types(void) 288 { 289 type_register_static(&pnv_pec_type_info); 290 } 291 292 type_init(pnv_pec_register_types); 293