1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "qapi/error.h" 11 #include "qemu/log.h" 12 #include "target/ppc/cpu.h" 13 #include "hw/ppc/fdt.h" 14 #include "hw/pci-host/pnv_phb4_regs.h" 15 #include "hw/pci-host/pnv_phb4.h" 16 #include "hw/ppc/pnv_xscom.h" 17 #include "hw/pci/pci_bridge.h" 18 #include "hw/pci/pci_bus.h" 19 #include "hw/ppc/pnv.h" 20 #include "hw/ppc/pnv_chip.h" 21 #include "hw/qdev-properties.h" 22 #include "sysemu/sysemu.h" 23 24 #include <libfdt.h> 25 26 #define phb_pec_error(pec, fmt, ...) \ 27 qemu_log_mask(LOG_GUEST_ERROR, "phb4_pec[%d:%d]: " fmt "\n", \ 28 (pec)->chip_id, (pec)->index, ## __VA_ARGS__) 29 30 31 static uint64_t pnv_pec_nest_xscom_read(void *opaque, hwaddr addr, 32 unsigned size) 33 { 34 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 35 uint32_t reg = addr >> 3; 36 37 /* All registers are readable */ 38 return pec->nest_regs[reg]; 39 } 40 41 static void pnv_pec_nest_xscom_write(void *opaque, hwaddr addr, 42 uint64_t val, unsigned size) 43 { 44 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 45 uint32_t reg = addr >> 3; 46 47 switch (reg) { 48 case PEC_NEST_DROP_PRIO_CTRL: 49 pec->nest_regs[reg] = val & PPC_BITMASK(0, 25); 50 break; 51 case PEC_NEST_PBCQ_ERR_INJECT: 52 pec->nest_regs[reg] = val & PPC_BITMASK(0, 11); 53 break; 54 case PEC_NEST_PCI_NEST_CLK_TRACE_CTL: 55 pec->nest_regs[reg] = val & PPC_BITMASK(0, 16); 56 break; 57 case PEC_NEST_PBCQ_PMON_CTRL: 58 pec->nest_regs[reg] = val & PPC_BITMASK(0, 37); 59 break; 60 case PEC_NEST_PBCQ_PBUS_ADDR_EXT: 61 pec->nest_regs[reg] = val & PPC_BITMASK(0, 6); 62 break; 63 case PEC_NEST_PBCQ_PRED_VEC_TIMEOUT: 64 pec->nest_regs[reg] = val & PPC_BITMASK(0, 15); 65 break; 66 case PEC_NEST_PBCQ_READ_STK_OVR: 67 pec->nest_regs[reg] = val & PPC_BITMASK(0, 48); 68 break; 69 case PEC_NEST_PBCQ_WRITE_STK_OVR: 70 case PEC_NEST_PBCQ_STORE_STK_OVR: 71 pec->nest_regs[reg] = val & PPC_BITMASK(0, 24); 72 break; 73 case PEC_NEST_PBCQ_RETRY_BKOFF_CTRL: 74 pec->nest_regs[reg] = val & PPC_BITMASK(0, 41); 75 break; 76 case PEC_NEST_PBCQ_HW_CONFIG: 77 case PEC_NEST_CAPP_CTRL: 78 pec->nest_regs[reg] = val; 79 break; 80 default: 81 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 82 addr, val); 83 } 84 } 85 86 static const MemoryRegionOps pnv_pec_nest_xscom_ops = { 87 .read = pnv_pec_nest_xscom_read, 88 .write = pnv_pec_nest_xscom_write, 89 .valid.min_access_size = 8, 90 .valid.max_access_size = 8, 91 .impl.min_access_size = 8, 92 .impl.max_access_size = 8, 93 .endianness = DEVICE_BIG_ENDIAN, 94 }; 95 96 static uint64_t pnv_pec_pci_xscom_read(void *opaque, hwaddr addr, 97 unsigned size) 98 { 99 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 100 uint32_t reg = addr >> 3; 101 102 /* All registers are readable */ 103 return pec->pci_regs[reg]; 104 } 105 106 static void pnv_pec_pci_xscom_write(void *opaque, hwaddr addr, 107 uint64_t val, unsigned size) 108 { 109 PnvPhb4PecState *pec = PNV_PHB4_PEC(opaque); 110 uint32_t reg = addr >> 3; 111 112 switch (reg) { 113 case PEC_PCI_PBAIB_HW_CONFIG: 114 pec->pci_regs[reg] = val & PPC_BITMASK(0, 42); 115 break; 116 case PEC_PCI_PBAIB_HW_OVR: 117 pec->pci_regs[reg] = val & PPC_BITMASK(0, 15); 118 break; 119 case PEC_PCI_PBAIB_READ_STK_OVR: 120 pec->pci_regs[reg] = val & PPC_BITMASK(0, 48); 121 break; 122 default: 123 phb_pec_error(pec, "%s @0x%"HWADDR_PRIx"=%"PRIx64"\n", __func__, 124 addr, val); 125 } 126 } 127 128 static const MemoryRegionOps pnv_pec_pci_xscom_ops = { 129 .read = pnv_pec_pci_xscom_read, 130 .write = pnv_pec_pci_xscom_write, 131 .valid.min_access_size = 8, 132 .valid.max_access_size = 8, 133 .impl.min_access_size = 8, 134 .impl.max_access_size = 8, 135 .endianness = DEVICE_BIG_ENDIAN, 136 }; 137 138 PnvPhb4PecState *pnv_pec_add_phb(PnvChip *chip, PnvPHB *phb, Error **errp) 139 { 140 PnvPhb4PecState *pecs = NULL; 141 int chip_id = phb->chip_id; 142 int index = phb->phb_id; 143 int i, j; 144 145 if (phb->version == 4) { 146 Pnv9Chip *chip9 = PNV9_CHIP(chip); 147 148 pecs = chip9->pecs; 149 } else if (phb->version == 5) { 150 Pnv10Chip *chip10 = PNV10_CHIP(chip); 151 152 pecs = chip10->pecs; 153 } else { 154 g_assert_not_reached(); 155 } 156 157 for (i = 0; i < chip->num_pecs; i++) { 158 /* 159 * For each PEC, check the amount of phbs it supports 160 * and see if the given phb4 index matches an index. 161 */ 162 PnvPhb4PecState *pec = &pecs[i]; 163 164 for (j = 0; j < pec->num_phbs; j++) { 165 if (index == pnv_phb4_pec_get_phb_id(pec, j)) { 166 pec->phbs[j] = phb; 167 phb->pec = pec; 168 return pec; 169 } 170 } 171 } 172 error_setg(errp, 173 "pnv-phb4 chip-id %d index %d didn't match any existing PEC", 174 chip_id, index); 175 176 return NULL; 177 } 178 179 static PnvPHB *pnv_pec_default_phb_realize(PnvPhb4PecState *pec, 180 int stack_no, 181 Error **errp) 182 { 183 PnvPHB *phb = PNV_PHB(qdev_new(TYPE_PNV_PHB)); 184 int phb_id = pnv_phb4_pec_get_phb_id(pec, stack_no); 185 186 object_property_add_child(OBJECT(pec), "phb[*]", OBJECT(phb)); 187 object_property_set_link(OBJECT(phb), "pec", OBJECT(pec), 188 &error_abort); 189 object_property_set_int(OBJECT(phb), "chip-id", pec->chip_id, 190 &error_fatal); 191 object_property_set_int(OBJECT(phb), "index", phb_id, 192 &error_fatal); 193 194 if (!sysbus_realize(SYS_BUS_DEVICE(phb), errp)) { 195 return NULL; 196 } 197 return phb; 198 } 199 200 static void pnv_pec_realize(DeviceState *dev, Error **errp) 201 { 202 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 203 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 204 char name[64]; 205 int i; 206 207 if (pec->index >= PNV_CHIP_GET_CLASS(pec->chip)->num_pecs) { 208 error_setg(errp, "invalid PEC index: %d", pec->index); 209 return; 210 } 211 212 pec->num_phbs = pecc->num_phbs[pec->index]; 213 214 /* Create PHBs if running with defaults */ 215 if (defaults_enabled()) { 216 g_assert(pec->num_phbs <= MAX_PHBS_PER_PEC); 217 for (i = 0; i < pec->num_phbs; i++) { 218 pec->phbs[i] = pnv_pec_default_phb_realize(pec, i, errp); 219 } 220 } 221 222 /* Initialize the XSCOM regions for the PEC registers */ 223 snprintf(name, sizeof(name), "xscom-pec-%d.%d-nest", pec->chip_id, 224 pec->index); 225 pnv_xscom_region_init(&pec->nest_regs_mr, OBJECT(dev), 226 &pnv_pec_nest_xscom_ops, pec, name, 227 PHB4_PEC_NEST_REGS_COUNT); 228 229 snprintf(name, sizeof(name), "xscom-pec-%d.%d-pci", pec->chip_id, 230 pec->index); 231 pnv_xscom_region_init(&pec->pci_regs_mr, OBJECT(dev), 232 &pnv_pec_pci_xscom_ops, pec, name, 233 PHB4_PEC_PCI_REGS_COUNT); 234 } 235 236 static int pnv_pec_dt_xscom(PnvXScomInterface *dev, void *fdt, 237 int xscom_offset) 238 { 239 PnvPhb4PecState *pec = PNV_PHB4_PEC(dev); 240 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(dev); 241 uint32_t nbase = pecc->xscom_nest_base(pec); 242 uint32_t pbase = pecc->xscom_pci_base(pec); 243 int offset, i; 244 char *name; 245 uint32_t reg[] = { 246 cpu_to_be32(nbase), 247 cpu_to_be32(pecc->xscom_nest_size), 248 cpu_to_be32(pbase), 249 cpu_to_be32(pecc->xscom_pci_size), 250 }; 251 252 name = g_strdup_printf("pbcq@%x", nbase); 253 offset = fdt_add_subnode(fdt, xscom_offset, name); 254 _FDT(offset); 255 g_free(name); 256 257 _FDT((fdt_setprop(fdt, offset, "reg", reg, sizeof(reg)))); 258 259 _FDT((fdt_setprop_cell(fdt, offset, "ibm,pec-index", pec->index))); 260 _FDT((fdt_setprop_cell(fdt, offset, "#address-cells", 1))); 261 _FDT((fdt_setprop_cell(fdt, offset, "#size-cells", 0))); 262 _FDT((fdt_setprop(fdt, offset, "compatible", pecc->compat, 263 pecc->compat_size))); 264 265 for (i = 0; i < pec->num_phbs; i++) { 266 int stk_offset; 267 268 if (!pec->phbs[i]) { 269 continue; 270 } 271 272 name = g_strdup_printf("stack@%x", i); 273 stk_offset = fdt_add_subnode(fdt, offset, name); 274 _FDT(stk_offset); 275 g_free(name); 276 _FDT((fdt_setprop(fdt, stk_offset, "compatible", pecc->stk_compat, 277 pecc->stk_compat_size))); 278 _FDT((fdt_setprop_cell(fdt, stk_offset, "reg", i))); 279 _FDT((fdt_setprop_cell(fdt, stk_offset, "ibm,phb-index", 280 pec->phbs[i]->phb_id))); 281 } 282 283 return 0; 284 } 285 286 static Property pnv_pec_properties[] = { 287 DEFINE_PROP_UINT32("index", PnvPhb4PecState, index, 0), 288 DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), 289 DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, 290 PnvChip *), 291 DEFINE_PROP_END_OF_LIST(), 292 }; 293 294 static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec) 295 { 296 return PNV9_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index; 297 } 298 299 static uint32_t pnv_pec_xscom_nest_base(PnvPhb4PecState *pec) 300 { 301 return PNV9_XSCOM_PEC_NEST_BASE + 0x400 * pec->index; 302 } 303 304 /* 305 * PEC0 -> 1 phb 306 * PEC1 -> 2 phb 307 * PEC2 -> 3 phbs 308 */ 309 static const uint32_t pnv_pec_num_phbs[] = { 1, 2, 3 }; 310 311 static void pnv_pec_class_init(ObjectClass *klass, void *data) 312 { 313 DeviceClass *dc = DEVICE_CLASS(klass); 314 PnvXScomInterfaceClass *xdc = PNV_XSCOM_INTERFACE_CLASS(klass); 315 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass); 316 static const char compat[] = "ibm,power9-pbcq"; 317 static const char stk_compat[] = "ibm,power9-phb-stack"; 318 319 xdc->dt_xscom = pnv_pec_dt_xscom; 320 321 dc->realize = pnv_pec_realize; 322 device_class_set_props(dc, pnv_pec_properties); 323 dc->user_creatable = false; 324 325 pecc->xscom_nest_base = pnv_pec_xscom_nest_base; 326 pecc->xscom_pci_base = pnv_pec_xscom_pci_base; 327 pecc->xscom_nest_size = PNV9_XSCOM_PEC_NEST_SIZE; 328 pecc->xscom_pci_size = PNV9_XSCOM_PEC_PCI_SIZE; 329 pecc->compat = compat; 330 pecc->compat_size = sizeof(compat); 331 pecc->stk_compat = stk_compat; 332 pecc->stk_compat_size = sizeof(stk_compat); 333 pecc->version = PNV_PHB4_VERSION; 334 pecc->phb_type = TYPE_PNV_PHB4; 335 pecc->num_phbs = pnv_pec_num_phbs; 336 } 337 338 static const TypeInfo pnv_pec_type_info = { 339 .name = TYPE_PNV_PHB4_PEC, 340 .parent = TYPE_DEVICE, 341 .instance_size = sizeof(PnvPhb4PecState), 342 .class_init = pnv_pec_class_init, 343 .class_size = sizeof(PnvPhb4PecClass), 344 .interfaces = (InterfaceInfo[]) { 345 { TYPE_PNV_XSCOM_INTERFACE }, 346 { } 347 } 348 }; 349 350 /* 351 * POWER10 definitions 352 */ 353 354 static uint32_t pnv_phb5_pec_xscom_pci_base(PnvPhb4PecState *pec) 355 { 356 return PNV10_XSCOM_PEC_PCI_BASE + 0x1000000 * pec->index; 357 } 358 359 static uint32_t pnv_phb5_pec_xscom_nest_base(PnvPhb4PecState *pec) 360 { 361 /* index goes down ... */ 362 return PNV10_XSCOM_PEC_NEST_BASE - 0x1000000 * pec->index; 363 } 364 365 /* 366 * PEC0 -> 3 stacks 367 * PEC1 -> 3 stacks 368 */ 369 static const uint32_t pnv_phb5_pec_num_stacks[] = { 3, 3 }; 370 371 static void pnv_phb5_pec_class_init(ObjectClass *klass, void *data) 372 { 373 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_CLASS(klass); 374 static const char compat[] = "ibm,power10-pbcq"; 375 static const char stk_compat[] = "ibm,power10-phb-stack"; 376 377 pecc->xscom_nest_base = pnv_phb5_pec_xscom_nest_base; 378 pecc->xscom_pci_base = pnv_phb5_pec_xscom_pci_base; 379 pecc->xscom_nest_size = PNV10_XSCOM_PEC_NEST_SIZE; 380 pecc->xscom_pci_size = PNV10_XSCOM_PEC_PCI_SIZE; 381 pecc->compat = compat; 382 pecc->compat_size = sizeof(compat); 383 pecc->stk_compat = stk_compat; 384 pecc->stk_compat_size = sizeof(stk_compat); 385 pecc->version = PNV_PHB5_VERSION; 386 pecc->phb_type = TYPE_PNV_PHB5; 387 pecc->num_phbs = pnv_phb5_pec_num_stacks; 388 } 389 390 static const TypeInfo pnv_phb5_pec_type_info = { 391 .name = TYPE_PNV_PHB5_PEC, 392 .parent = TYPE_PNV_PHB4_PEC, 393 .instance_size = sizeof(PnvPhb4PecState), 394 .class_init = pnv_phb5_pec_class_init, 395 .class_size = sizeof(PnvPhb4PecClass), 396 .interfaces = (InterfaceInfo[]) { 397 { TYPE_PNV_XSCOM_INTERFACE }, 398 { } 399 } 400 }; 401 402 static void pnv_pec_register_types(void) 403 { 404 type_register_static(&pnv_pec_type_info); 405 type_register_static(&pnv_phb5_pec_type_info); 406 } 407 408 type_init(pnv_pec_register_types); 409