1 /* 2 * QEMU PowerPC PowerNV (POWER9) PHB4 model 3 * 4 * Copyright (c) 2018-2020, IBM Corporation. 5 * 6 * This code is licensed under the GPL version 2 or later. See the 7 * COPYING file in the top-level directory. 8 */ 9 #include "qemu/osdep.h" 10 #include "qemu/log.h" 11 #include "qapi/visitor.h" 12 #include "qapi/error.h" 13 #include "qemu-common.h" 14 #include "monitor/monitor.h" 15 #include "target/ppc/cpu.h" 16 #include "hw/pci-host/pnv_phb4_regs.h" 17 #include "hw/pci-host/pnv_phb4.h" 18 #include "hw/pci/pcie_host.h" 19 #include "hw/pci/pcie_port.h" 20 #include "hw/ppc/pnv.h" 21 #include "hw/ppc/pnv_xscom.h" 22 #include "hw/irq.h" 23 #include "hw/qdev-properties.h" 24 #include "qom/object.h" 25 #include "sysemu/sysemu.h" 26 #include "trace.h" 27 28 #define phb_error(phb, fmt, ...) \ 29 qemu_log_mask(LOG_GUEST_ERROR, "phb4[%d:%d]: " fmt "\n", \ 30 (phb)->chip_id, (phb)->phb_id, ## __VA_ARGS__) 31 32 /* 33 * QEMU version of the GETFIELD/SETFIELD macros 34 * 35 * These are common with the PnvXive model. 36 */ 37 static inline uint64_t GETFIELD(uint64_t mask, uint64_t word) 38 { 39 return (word & mask) >> ctz64(mask); 40 } 41 42 static inline uint64_t SETFIELD(uint64_t mask, uint64_t word, 43 uint64_t value) 44 { 45 return (word & ~mask) | ((value << ctz64(mask)) & mask); 46 } 47 48 static PCIDevice *pnv_phb4_find_cfg_dev(PnvPHB4 *phb) 49 { 50 PCIHostState *pci = PCI_HOST_BRIDGE(phb); 51 uint64_t addr = phb->regs[PHB_CONFIG_ADDRESS >> 3]; 52 uint8_t bus, devfn; 53 54 if (!(addr >> 63)) { 55 return NULL; 56 } 57 bus = (addr >> 52) & 0xff; 58 devfn = (addr >> 44) & 0xff; 59 60 /* We don't access the root complex this way */ 61 if (bus == 0 && devfn == 0) { 62 return NULL; 63 } 64 return pci_find_device(pci->bus, bus, devfn); 65 } 66 67 /* 68 * The CONFIG_DATA register expects little endian accesses, but as the 69 * region is big endian, we have to swap the value. 70 */ 71 static void pnv_phb4_config_write(PnvPHB4 *phb, unsigned off, 72 unsigned size, uint64_t val) 73 { 74 uint32_t cfg_addr, limit; 75 PCIDevice *pdev; 76 77 pdev = pnv_phb4_find_cfg_dev(phb); 78 if (!pdev) { 79 return; 80 } 81 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; 82 cfg_addr |= off; 83 limit = pci_config_size(pdev); 84 if (limit <= cfg_addr) { 85 /* 86 * conventional pci device can be behind pcie-to-pci bridge. 87 * 256 <= addr < 4K has no effects. 88 */ 89 return; 90 } 91 switch (size) { 92 case 1: 93 break; 94 case 2: 95 val = bswap16(val); 96 break; 97 case 4: 98 val = bswap32(val); 99 break; 100 default: 101 g_assert_not_reached(); 102 } 103 pci_host_config_write_common(pdev, cfg_addr, limit, val, size); 104 } 105 106 static uint64_t pnv_phb4_config_read(PnvPHB4 *phb, unsigned off, 107 unsigned size) 108 { 109 uint32_t cfg_addr, limit; 110 PCIDevice *pdev; 111 uint64_t val; 112 113 pdev = pnv_phb4_find_cfg_dev(phb); 114 if (!pdev) { 115 return ~0ull; 116 } 117 cfg_addr = (phb->regs[PHB_CONFIG_ADDRESS >> 3] >> 32) & 0xffc; 118 cfg_addr |= off; 119 limit = pci_config_size(pdev); 120 if (limit <= cfg_addr) { 121 /* 122 * conventional pci device can be behind pcie-to-pci bridge. 123 * 256 <= addr < 4K has no effects. 124 */ 125 return ~0ull; 126 } 127 val = pci_host_config_read_common(pdev, cfg_addr, limit, size); 128 switch (size) { 129 case 1: 130 return val; 131 case 2: 132 return bswap16(val); 133 case 4: 134 return bswap32(val); 135 default: 136 g_assert_not_reached(); 137 } 138 } 139 140 /* 141 * Root complex register accesses are memory mapped. 142 */ 143 static void pnv_phb4_rc_config_write(PnvPHB4 *phb, unsigned off, 144 unsigned size, uint64_t val) 145 { 146 PCIHostState *pci = PCI_HOST_BRIDGE(phb); 147 PCIDevice *pdev; 148 149 if (size != 4) { 150 phb_error(phb, "rc_config_write invalid size %d\n", size); 151 return; 152 } 153 154 pdev = pci_find_device(pci->bus, 0, 0); 155 if (!pdev) { 156 phb_error(phb, "rc_config_write device not found\n"); 157 return; 158 } 159 160 pci_host_config_write_common(pdev, off, PHB_RC_CONFIG_SIZE, 161 bswap32(val), 4); 162 } 163 164 static uint64_t pnv_phb4_rc_config_read(PnvPHB4 *phb, unsigned off, 165 unsigned size) 166 { 167 PCIHostState *pci = PCI_HOST_BRIDGE(phb); 168 PCIDevice *pdev; 169 uint64_t val; 170 171 if (size != 4) { 172 phb_error(phb, "rc_config_read invalid size %d\n", size); 173 return ~0ull; 174 } 175 176 pdev = pci_find_device(pci->bus, 0, 0); 177 if (!pdev) { 178 phb_error(phb, "rc_config_read device not found\n"); 179 return ~0ull; 180 } 181 182 val = pci_host_config_read_common(pdev, off, PHB_RC_CONFIG_SIZE, 4); 183 return bswap32(val); 184 } 185 186 static void pnv_phb4_check_mbt(PnvPHB4 *phb, uint32_t index) 187 { 188 uint64_t base, start, size, mbe0, mbe1; 189 MemoryRegion *parent; 190 char name[64]; 191 192 /* Unmap first */ 193 if (memory_region_is_mapped(&phb->mr_mmio[index])) { 194 /* Should we destroy it in RCU friendly way... ? */ 195 memory_region_del_subregion(phb->mr_mmio[index].container, 196 &phb->mr_mmio[index]); 197 } 198 199 /* Get table entry */ 200 mbe0 = phb->ioda_MBT[(index << 1)]; 201 mbe1 = phb->ioda_MBT[(index << 1) + 1]; 202 203 if (!(mbe0 & IODA3_MBT0_ENABLE)) { 204 return; 205 } 206 207 /* Grab geometry from registers */ 208 base = GETFIELD(IODA3_MBT0_BASE_ADDR, mbe0) << 12; 209 size = GETFIELD(IODA3_MBT1_MASK, mbe1) << 12; 210 size |= 0xff00000000000000ull; 211 size = ~size + 1; 212 213 /* Calculate PCI side start address based on M32/M64 window type */ 214 if (mbe0 & IODA3_MBT0_TYPE_M32) { 215 start = phb->regs[PHB_M32_START_ADDR >> 3]; 216 if ((start + size) > 0x100000000ull) { 217 phb_error(phb, "M32 set beyond 4GB boundary !"); 218 size = 0x100000000 - start; 219 } 220 } else { 221 start = base | (phb->regs[PHB_M64_UPPER_BITS >> 3]); 222 } 223 224 /* TODO: Figure out how to implemet/decode AOMASK */ 225 226 /* Check if it matches an enabled MMIO region in the PEC stack */ 227 if (memory_region_is_mapped(&phb->stack->mmbar0) && 228 base >= phb->stack->mmio0_base && 229 (base + size) <= (phb->stack->mmio0_base + phb->stack->mmio0_size)) { 230 parent = &phb->stack->mmbar0; 231 base -= phb->stack->mmio0_base; 232 } else if (memory_region_is_mapped(&phb->stack->mmbar1) && 233 base >= phb->stack->mmio1_base && 234 (base + size) <= (phb->stack->mmio1_base + phb->stack->mmio1_size)) { 235 parent = &phb->stack->mmbar1; 236 base -= phb->stack->mmio1_base; 237 } else { 238 phb_error(phb, "PHB MBAR %d out of parent bounds", index); 239 return; 240 } 241 242 /* Create alias (better name ?) */ 243 snprintf(name, sizeof(name), "phb4-mbar%d", index); 244 memory_region_init_alias(&phb->mr_mmio[index], OBJECT(phb), name, 245 &phb->pci_mmio, start, size); 246 memory_region_add_subregion(parent, base, &phb->mr_mmio[index]); 247 } 248 249 static void pnv_phb4_check_all_mbt(PnvPHB4 *phb) 250 { 251 uint64_t i; 252 uint32_t num_windows = phb->big_phb ? PNV_PHB4_MAX_MMIO_WINDOWS : 253 PNV_PHB4_MIN_MMIO_WINDOWS; 254 255 for (i = 0; i < num_windows; i++) { 256 pnv_phb4_check_mbt(phb, i); 257 } 258 } 259 260 static uint64_t *pnv_phb4_ioda_access(PnvPHB4 *phb, 261 unsigned *out_table, unsigned *out_idx) 262 { 263 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3]; 264 unsigned int index = GETFIELD(PHB_IODA_AD_TADR, adreg); 265 unsigned int table = GETFIELD(PHB_IODA_AD_TSEL, adreg); 266 unsigned int mask; 267 uint64_t *tptr = NULL; 268 269 switch (table) { 270 case IODA3_TBL_LIST: 271 tptr = phb->ioda_LIST; 272 mask = 7; 273 break; 274 case IODA3_TBL_MIST: 275 tptr = phb->ioda_MIST; 276 mask = phb->big_phb ? PNV_PHB4_MAX_MIST : (PNV_PHB4_MAX_MIST >> 1); 277 mask -= 1; 278 break; 279 case IODA3_TBL_RCAM: 280 mask = phb->big_phb ? 127 : 63; 281 break; 282 case IODA3_TBL_MRT: 283 mask = phb->big_phb ? 15 : 7; 284 break; 285 case IODA3_TBL_PESTA: 286 case IODA3_TBL_PESTB: 287 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1); 288 mask -= 1; 289 break; 290 case IODA3_TBL_TVT: 291 tptr = phb->ioda_TVT; 292 mask = phb->big_phb ? PNV_PHB4_MAX_TVEs : (PNV_PHB4_MAX_TVEs >> 1); 293 mask -= 1; 294 break; 295 case IODA3_TBL_TCR: 296 case IODA3_TBL_TDR: 297 mask = phb->big_phb ? 1023 : 511; 298 break; 299 case IODA3_TBL_MBT: 300 tptr = phb->ioda_MBT; 301 mask = phb->big_phb ? PNV_PHB4_MAX_MBEs : (PNV_PHB4_MAX_MBEs >> 1); 302 mask -= 1; 303 break; 304 case IODA3_TBL_MDT: 305 tptr = phb->ioda_MDT; 306 mask = phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1); 307 mask -= 1; 308 break; 309 case IODA3_TBL_PEEV: 310 tptr = phb->ioda_PEEV; 311 mask = phb->big_phb ? PNV_PHB4_MAX_PEEVs : (PNV_PHB4_MAX_PEEVs >> 1); 312 mask -= 1; 313 break; 314 default: 315 phb_error(phb, "invalid IODA table %d", table); 316 return NULL; 317 } 318 index &= mask; 319 if (out_idx) { 320 *out_idx = index; 321 } 322 if (out_table) { 323 *out_table = table; 324 } 325 if (tptr) { 326 tptr += index; 327 } 328 if (adreg & PHB_IODA_AD_AUTOINC) { 329 index = (index + 1) & mask; 330 adreg = SETFIELD(PHB_IODA_AD_TADR, adreg, index); 331 } 332 333 phb->regs[PHB_IODA_ADDR >> 3] = adreg; 334 return tptr; 335 } 336 337 static uint64_t pnv_phb4_ioda_read(PnvPHB4 *phb) 338 { 339 unsigned table, idx; 340 uint64_t *tptr; 341 342 tptr = pnv_phb4_ioda_access(phb, &table, &idx); 343 if (!tptr) { 344 /* Special PESTA case */ 345 if (table == IODA3_TBL_PESTA) { 346 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 1)) << 63; 347 } else if (table == IODA3_TBL_PESTB) { 348 return ((uint64_t)(phb->ioda_PEST_AB[idx] & 2)) << 62; 349 } 350 /* Return 0 on unsupported tables, not ff's */ 351 return 0; 352 } 353 return *tptr; 354 } 355 356 static void pnv_phb4_ioda_write(PnvPHB4 *phb, uint64_t val) 357 { 358 unsigned table, idx; 359 uint64_t *tptr; 360 361 tptr = pnv_phb4_ioda_access(phb, &table, &idx); 362 if (!tptr) { 363 /* Special PESTA case */ 364 if (table == IODA3_TBL_PESTA) { 365 phb->ioda_PEST_AB[idx] &= ~1; 366 phb->ioda_PEST_AB[idx] |= (val >> 63) & 1; 367 } else if (table == IODA3_TBL_PESTB) { 368 phb->ioda_PEST_AB[idx] &= ~2; 369 phb->ioda_PEST_AB[idx] |= (val >> 62) & 2; 370 } 371 return; 372 } 373 374 /* Handle side effects */ 375 switch (table) { 376 case IODA3_TBL_LIST: 377 break; 378 case IODA3_TBL_MIST: { 379 /* Special mask for MIST partial write */ 380 uint64_t adreg = phb->regs[PHB_IODA_ADDR >> 3]; 381 uint32_t mmask = GETFIELD(PHB_IODA_AD_MIST_PWV, adreg); 382 uint64_t v = *tptr; 383 if (mmask == 0) { 384 mmask = 0xf; 385 } 386 if (mmask & 8) { 387 v &= 0x0000ffffffffffffull; 388 v |= 0xcfff000000000000ull & val; 389 } 390 if (mmask & 4) { 391 v &= 0xffff0000ffffffffull; 392 v |= 0x0000cfff00000000ull & val; 393 } 394 if (mmask & 2) { 395 v &= 0xffffffff0000ffffull; 396 v |= 0x00000000cfff0000ull & val; 397 } 398 if (mmask & 1) { 399 v &= 0xffffffffffff0000ull; 400 v |= 0x000000000000cfffull & val; 401 } 402 *tptr = v; 403 break; 404 } 405 case IODA3_TBL_MBT: 406 *tptr = val; 407 408 /* Copy accross the valid bit to the other half */ 409 phb->ioda_MBT[idx ^ 1] &= 0x7fffffffffffffffull; 410 phb->ioda_MBT[idx ^ 1] |= 0x8000000000000000ull & val; 411 412 /* Update mappings */ 413 pnv_phb4_check_mbt(phb, idx >> 1); 414 break; 415 default: 416 *tptr = val; 417 } 418 } 419 420 static void pnv_phb4_rtc_invalidate(PnvPHB4 *phb, uint64_t val) 421 { 422 PnvPhb4DMASpace *ds; 423 424 /* Always invalidate all for now ... */ 425 QLIST_FOREACH(ds, &phb->dma_spaces, list) { 426 ds->pe_num = PHB_INVALID_PE; 427 } 428 } 429 430 static void pnv_phb4_update_msi_regions(PnvPhb4DMASpace *ds) 431 { 432 uint64_t cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3]; 433 434 if (cfg & PHB_PHB4C_32BIT_MSI_EN) { 435 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) { 436 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), 437 0xffff0000, &ds->msi32_mr); 438 } 439 } else { 440 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi32_mr))) { 441 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), 442 &ds->msi32_mr); 443 } 444 } 445 446 if (cfg & PHB_PHB4C_64BIT_MSI_EN) { 447 if (!memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) { 448 memory_region_add_subregion(MEMORY_REGION(&ds->dma_mr), 449 (1ull << 60), &ds->msi64_mr); 450 } 451 } else { 452 if (memory_region_is_mapped(MEMORY_REGION(&ds->msi64_mr))) { 453 memory_region_del_subregion(MEMORY_REGION(&ds->dma_mr), 454 &ds->msi64_mr); 455 } 456 } 457 } 458 459 static void pnv_phb4_update_all_msi_regions(PnvPHB4 *phb) 460 { 461 PnvPhb4DMASpace *ds; 462 463 QLIST_FOREACH(ds, &phb->dma_spaces, list) { 464 pnv_phb4_update_msi_regions(ds); 465 } 466 } 467 468 static void pnv_phb4_update_xsrc(PnvPHB4 *phb) 469 { 470 int shift, flags, i, lsi_base; 471 XiveSource *xsrc = &phb->xsrc; 472 473 /* The XIVE source characteristics can be set at run time */ 474 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_PGSZ_64K) { 475 shift = XIVE_ESB_64K; 476 } else { 477 shift = XIVE_ESB_4K; 478 } 479 if (phb->regs[PHB_CTRLR >> 3] & PHB_CTRLR_IRQ_STORE_EOI) { 480 flags = XIVE_SRC_STORE_EOI; 481 } else { 482 flags = 0; 483 } 484 485 phb->xsrc.esb_shift = shift; 486 phb->xsrc.esb_flags = flags; 487 488 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); 489 lsi_base <<= 3; 490 491 /* TODO: handle reset values of PHB_LSI_SRC_ID */ 492 if (!lsi_base) { 493 return; 494 } 495 496 /* TODO: need a xive_source_irq_reset_lsi() */ 497 bitmap_zero(xsrc->lsi_map, xsrc->nr_irqs); 498 499 for (i = 0; i < xsrc->nr_irqs; i++) { 500 bool msi = (i < lsi_base || i >= (lsi_base + 8)); 501 if (!msi) { 502 xive_source_irq_set_lsi(xsrc, i); 503 } 504 } 505 } 506 507 static void pnv_phb4_reg_write(void *opaque, hwaddr off, uint64_t val, 508 unsigned size) 509 { 510 PnvPHB4 *phb = PNV_PHB4(opaque); 511 bool changed; 512 513 /* Special case outbound configuration data */ 514 if ((off & 0xfffc) == PHB_CONFIG_DATA) { 515 pnv_phb4_config_write(phb, off & 0x3, size, val); 516 return; 517 } 518 519 /* Special case RC configuration space */ 520 if ((off & 0xf800) == PHB_RC_CONFIG_BASE) { 521 pnv_phb4_rc_config_write(phb, off & 0x7ff, size, val); 522 return; 523 } 524 525 /* Other registers are 64-bit only */ 526 if (size != 8 || off & 0x7) { 527 phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d", 528 off, size); 529 return; 530 } 531 532 /* Handle masking */ 533 switch (off) { 534 case PHB_LSI_SOURCE_ID: 535 val &= PHB_LSI_SRC_ID; 536 break; 537 case PHB_M64_UPPER_BITS: 538 val &= 0xff00000000000000ull; 539 break; 540 /* TCE Kill */ 541 case PHB_TCE_KILL: 542 /* Clear top 3 bits which HW does to indicate successful queuing */ 543 val &= ~(PHB_TCE_KILL_ALL | PHB_TCE_KILL_PE | PHB_TCE_KILL_ONE); 544 break; 545 case PHB_Q_DMA_R: 546 /* 547 * This is enough logic to make SW happy but we aren't 548 * actually quiescing the DMAs 549 */ 550 if (val & PHB_Q_DMA_R_AUTORESET) { 551 val = 0; 552 } else { 553 val &= PHB_Q_DMA_R_QUIESCE_DMA; 554 } 555 break; 556 /* LEM stuff */ 557 case PHB_LEM_FIR_AND_MASK: 558 phb->regs[PHB_LEM_FIR_ACCUM >> 3] &= val; 559 return; 560 case PHB_LEM_FIR_OR_MASK: 561 phb->regs[PHB_LEM_FIR_ACCUM >> 3] |= val; 562 return; 563 case PHB_LEM_ERROR_AND_MASK: 564 phb->regs[PHB_LEM_ERROR_MASK >> 3] &= val; 565 return; 566 case PHB_LEM_ERROR_OR_MASK: 567 phb->regs[PHB_LEM_ERROR_MASK >> 3] |= val; 568 return; 569 case PHB_LEM_WOF: 570 val = 0; 571 break; 572 /* TODO: More regs ..., maybe create a table with masks... */ 573 574 /* Read only registers */ 575 case PHB_CPU_LOADSTORE_STATUS: 576 case PHB_ETU_ERR_SUMMARY: 577 case PHB_PHB4_GEN_CAP: 578 case PHB_PHB4_TCE_CAP: 579 case PHB_PHB4_IRQ_CAP: 580 case PHB_PHB4_EEH_CAP: 581 return; 582 } 583 584 /* Record whether it changed */ 585 changed = phb->regs[off >> 3] != val; 586 587 /* Store in register cache first */ 588 phb->regs[off >> 3] = val; 589 590 /* Handle side effects */ 591 switch (off) { 592 case PHB_PHB4_CONFIG: 593 if (changed) { 594 pnv_phb4_update_all_msi_regions(phb); 595 } 596 break; 597 case PHB_M32_START_ADDR: 598 case PHB_M64_UPPER_BITS: 599 if (changed) { 600 pnv_phb4_check_all_mbt(phb); 601 } 602 break; 603 604 /* IODA table accesses */ 605 case PHB_IODA_DATA0: 606 pnv_phb4_ioda_write(phb, val); 607 break; 608 609 /* RTC invalidation */ 610 case PHB_RTC_INVALIDATE: 611 pnv_phb4_rtc_invalidate(phb, val); 612 break; 613 614 /* PHB Control (Affects XIVE source) */ 615 case PHB_CTRLR: 616 case PHB_LSI_SOURCE_ID: 617 pnv_phb4_update_xsrc(phb); 618 break; 619 620 /* Silent simple writes */ 621 case PHB_ASN_CMPM: 622 case PHB_CONFIG_ADDRESS: 623 case PHB_IODA_ADDR: 624 case PHB_TCE_KILL: 625 case PHB_TCE_SPEC_CTL: 626 case PHB_PEST_BAR: 627 case PHB_PELTV_BAR: 628 case PHB_RTT_BAR: 629 case PHB_LEM_FIR_ACCUM: 630 case PHB_LEM_ERROR_MASK: 631 case PHB_LEM_ACTION0: 632 case PHB_LEM_ACTION1: 633 case PHB_TCE_TAG_ENABLE: 634 case PHB_INT_NOTIFY_ADDR: 635 case PHB_INT_NOTIFY_INDEX: 636 case PHB_DMARD_SYNC: 637 break; 638 639 /* Noise on anything else */ 640 default: 641 qemu_log_mask(LOG_UNIMP, "phb4: reg_write 0x%"PRIx64"=%"PRIx64"\n", 642 off, val); 643 } 644 } 645 646 static uint64_t pnv_phb4_reg_read(void *opaque, hwaddr off, unsigned size) 647 { 648 PnvPHB4 *phb = PNV_PHB4(opaque); 649 uint64_t val; 650 651 if ((off & 0xfffc) == PHB_CONFIG_DATA) { 652 return pnv_phb4_config_read(phb, off & 0x3, size); 653 } 654 655 /* Special case RC configuration space */ 656 if ((off & 0xf800) == PHB_RC_CONFIG_BASE) { 657 return pnv_phb4_rc_config_read(phb, off & 0x7ff, size); 658 } 659 660 /* Other registers are 64-bit only */ 661 if (size != 8 || off & 0x7) { 662 phb_error(phb, "Invalid register access, offset: 0x%"PRIx64" size: %d", 663 off, size); 664 return ~0ull; 665 } 666 667 /* Default read from cache */ 668 val = phb->regs[off >> 3]; 669 670 switch (off) { 671 case PHB_VERSION: 672 return phb->version; 673 674 /* Read-only */ 675 case PHB_PHB4_GEN_CAP: 676 return 0xe4b8000000000000ull; 677 case PHB_PHB4_TCE_CAP: 678 return phb->big_phb ? 0x4008440000000400ull : 0x2008440000000200ull; 679 case PHB_PHB4_IRQ_CAP: 680 return phb->big_phb ? 0x0800000000001000ull : 0x0800000000000800ull; 681 case PHB_PHB4_EEH_CAP: 682 return phb->big_phb ? 0x2000000000000000ull : 0x1000000000000000ull; 683 684 /* IODA table accesses */ 685 case PHB_IODA_DATA0: 686 return pnv_phb4_ioda_read(phb); 687 688 /* Link training always appears trained */ 689 case PHB_PCIE_DLP_TRAIN_CTL: 690 /* TODO: Do something sensible with speed ? */ 691 return PHB_PCIE_DLP_INBAND_PRESENCE | PHB_PCIE_DLP_TL_LINKACT; 692 693 /* DMA read sync: make it look like it's complete */ 694 case PHB_DMARD_SYNC: 695 return PHB_DMARD_SYNC_COMPLETE; 696 697 /* Silent simple reads */ 698 case PHB_LSI_SOURCE_ID: 699 case PHB_CPU_LOADSTORE_STATUS: 700 case PHB_ASN_CMPM: 701 case PHB_PHB4_CONFIG: 702 case PHB_M32_START_ADDR: 703 case PHB_CONFIG_ADDRESS: 704 case PHB_IODA_ADDR: 705 case PHB_RTC_INVALIDATE: 706 case PHB_TCE_KILL: 707 case PHB_TCE_SPEC_CTL: 708 case PHB_PEST_BAR: 709 case PHB_PELTV_BAR: 710 case PHB_RTT_BAR: 711 case PHB_M64_UPPER_BITS: 712 case PHB_CTRLR: 713 case PHB_LEM_FIR_ACCUM: 714 case PHB_LEM_ERROR_MASK: 715 case PHB_LEM_ACTION0: 716 case PHB_LEM_ACTION1: 717 case PHB_TCE_TAG_ENABLE: 718 case PHB_INT_NOTIFY_ADDR: 719 case PHB_INT_NOTIFY_INDEX: 720 case PHB_Q_DMA_R: 721 case PHB_ETU_ERR_SUMMARY: 722 break; 723 724 /* Noise on anything else */ 725 default: 726 qemu_log_mask(LOG_UNIMP, "phb4: reg_read 0x%"PRIx64"=%"PRIx64"\n", 727 off, val); 728 } 729 return val; 730 } 731 732 static const MemoryRegionOps pnv_phb4_reg_ops = { 733 .read = pnv_phb4_reg_read, 734 .write = pnv_phb4_reg_write, 735 .valid.min_access_size = 1, 736 .valid.max_access_size = 8, 737 .impl.min_access_size = 1, 738 .impl.max_access_size = 8, 739 .endianness = DEVICE_BIG_ENDIAN, 740 }; 741 742 static uint64_t pnv_phb4_xscom_read(void *opaque, hwaddr addr, unsigned size) 743 { 744 PnvPHB4 *phb = PNV_PHB4(opaque); 745 uint32_t reg = addr >> 3; 746 uint64_t val; 747 hwaddr offset; 748 749 switch (reg) { 750 case PHB_SCOM_HV_IND_ADDR: 751 return phb->scom_hv_ind_addr_reg; 752 753 case PHB_SCOM_HV_IND_DATA: 754 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) { 755 phb_error(phb, "Invalid indirect address"); 756 return ~0ull; 757 } 758 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8; 759 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg); 760 val = pnv_phb4_reg_read(phb, offset, size); 761 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) { 762 offset += size; 763 offset &= 0x3fff; 764 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, 765 phb->scom_hv_ind_addr_reg, 766 offset); 767 } 768 return val; 769 case PHB_SCOM_ETU_LEM_FIR: 770 case PHB_SCOM_ETU_LEM_FIR_AND: 771 case PHB_SCOM_ETU_LEM_FIR_OR: 772 case PHB_SCOM_ETU_LEM_FIR_MSK: 773 case PHB_SCOM_ETU_LEM_ERR_MSK_AND: 774 case PHB_SCOM_ETU_LEM_ERR_MSK_OR: 775 case PHB_SCOM_ETU_LEM_ACT0: 776 case PHB_SCOM_ETU_LEM_ACT1: 777 case PHB_SCOM_ETU_LEM_WOF: 778 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM; 779 return pnv_phb4_reg_read(phb, offset, size); 780 case PHB_SCOM_ETU_PMON_CONFIG: 781 case PHB_SCOM_ETU_PMON_CTR0: 782 case PHB_SCOM_ETU_PMON_CTR1: 783 case PHB_SCOM_ETU_PMON_CTR2: 784 case PHB_SCOM_ETU_PMON_CTR3: 785 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG; 786 return pnv_phb4_reg_read(phb, offset, size); 787 788 default: 789 qemu_log_mask(LOG_UNIMP, "phb4: xscom_read 0x%"HWADDR_PRIx"\n", addr); 790 return ~0ull; 791 } 792 } 793 794 static void pnv_phb4_xscom_write(void *opaque, hwaddr addr, 795 uint64_t val, unsigned size) 796 { 797 PnvPHB4 *phb = PNV_PHB4(opaque); 798 uint32_t reg = addr >> 3; 799 hwaddr offset; 800 801 switch (reg) { 802 case PHB_SCOM_HV_IND_ADDR: 803 phb->scom_hv_ind_addr_reg = val & 0xe000000000001fff; 804 break; 805 case PHB_SCOM_HV_IND_DATA: 806 if (!(phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_VALID)) { 807 phb_error(phb, "Invalid indirect address"); 808 break; 809 } 810 size = (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_4B) ? 4 : 8; 811 offset = GETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, phb->scom_hv_ind_addr_reg); 812 pnv_phb4_reg_write(phb, offset, val, size); 813 if (phb->scom_hv_ind_addr_reg & PHB_SCOM_HV_IND_ADDR_AUTOINC) { 814 offset += size; 815 offset &= 0x3fff; 816 phb->scom_hv_ind_addr_reg = SETFIELD(PHB_SCOM_HV_IND_ADDR_ADDR, 817 phb->scom_hv_ind_addr_reg, 818 offset); 819 } 820 break; 821 case PHB_SCOM_ETU_LEM_FIR: 822 case PHB_SCOM_ETU_LEM_FIR_AND: 823 case PHB_SCOM_ETU_LEM_FIR_OR: 824 case PHB_SCOM_ETU_LEM_FIR_MSK: 825 case PHB_SCOM_ETU_LEM_ERR_MSK_AND: 826 case PHB_SCOM_ETU_LEM_ERR_MSK_OR: 827 case PHB_SCOM_ETU_LEM_ACT0: 828 case PHB_SCOM_ETU_LEM_ACT1: 829 case PHB_SCOM_ETU_LEM_WOF: 830 offset = ((reg - PHB_SCOM_ETU_LEM_FIR) << 3) + PHB_LEM_FIR_ACCUM; 831 pnv_phb4_reg_write(phb, offset, val, size); 832 break; 833 case PHB_SCOM_ETU_PMON_CONFIG: 834 case PHB_SCOM_ETU_PMON_CTR0: 835 case PHB_SCOM_ETU_PMON_CTR1: 836 case PHB_SCOM_ETU_PMON_CTR2: 837 case PHB_SCOM_ETU_PMON_CTR3: 838 offset = ((reg - PHB_SCOM_ETU_PMON_CONFIG) << 3) + PHB_PERFMON_CONFIG; 839 pnv_phb4_reg_write(phb, offset, val, size); 840 break; 841 default: 842 qemu_log_mask(LOG_UNIMP, "phb4: xscom_write 0x%"HWADDR_PRIx 843 "=%"PRIx64"\n", addr, val); 844 } 845 } 846 847 const MemoryRegionOps pnv_phb4_xscom_ops = { 848 .read = pnv_phb4_xscom_read, 849 .write = pnv_phb4_xscom_write, 850 .valid.min_access_size = 8, 851 .valid.max_access_size = 8, 852 .impl.min_access_size = 8, 853 .impl.max_access_size = 8, 854 .endianness = DEVICE_BIG_ENDIAN, 855 }; 856 857 static int pnv_phb4_map_irq(PCIDevice *pci_dev, int irq_num) 858 { 859 /* Check that out properly ... */ 860 return irq_num & 3; 861 } 862 863 static void pnv_phb4_set_irq(void *opaque, int irq_num, int level) 864 { 865 PnvPHB4 *phb = PNV_PHB4(opaque); 866 uint32_t lsi_base; 867 868 /* LSI only ... */ 869 if (irq_num > 3) { 870 phb_error(phb, "IRQ %x is not an LSI", irq_num); 871 } 872 lsi_base = GETFIELD(PHB_LSI_SRC_ID, phb->regs[PHB_LSI_SOURCE_ID >> 3]); 873 lsi_base <<= 3; 874 qemu_set_irq(phb->qirqs[lsi_base + irq_num], level); 875 } 876 877 static bool pnv_phb4_resolve_pe(PnvPhb4DMASpace *ds) 878 { 879 uint64_t rtt, addr; 880 uint16_t rte; 881 int bus_num; 882 int num_PEs; 883 884 /* Already resolved ? */ 885 if (ds->pe_num != PHB_INVALID_PE) { 886 return true; 887 } 888 889 /* We need to lookup the RTT */ 890 rtt = ds->phb->regs[PHB_RTT_BAR >> 3]; 891 if (!(rtt & PHB_RTT_BAR_ENABLE)) { 892 phb_error(ds->phb, "DMA with RTT BAR disabled !"); 893 /* Set error bits ? fence ? ... */ 894 return false; 895 } 896 897 /* Read RTE */ 898 bus_num = pci_bus_num(ds->bus); 899 addr = rtt & PHB_RTT_BASE_ADDRESS_MASK; 900 addr += 2 * PCI_BUILD_BDF(bus_num, ds->devfn); 901 if (dma_memory_read(&address_space_memory, addr, &rte, 902 sizeof(rte), MEMTXATTRS_UNSPECIFIED)) { 903 phb_error(ds->phb, "Failed to read RTT entry at 0x%"PRIx64, addr); 904 /* Set error bits ? fence ? ... */ 905 return false; 906 } 907 rte = be16_to_cpu(rte); 908 909 /* Fail upon reading of invalid PE# */ 910 num_PEs = ds->phb->big_phb ? PNV_PHB4_MAX_PEs : (PNV_PHB4_MAX_PEs >> 1); 911 if (rte >= num_PEs) { 912 phb_error(ds->phb, "RTE for RID 0x%x invalid (%04x", ds->devfn, rte); 913 rte &= num_PEs - 1; 914 } 915 ds->pe_num = rte; 916 return true; 917 } 918 919 static void pnv_phb4_translate_tve(PnvPhb4DMASpace *ds, hwaddr addr, 920 bool is_write, uint64_t tve, 921 IOMMUTLBEntry *tlb) 922 { 923 uint64_t tta = GETFIELD(IODA3_TVT_TABLE_ADDR, tve); 924 int32_t lev = GETFIELD(IODA3_TVT_NUM_LEVELS, tve); 925 uint32_t tts = GETFIELD(IODA3_TVT_TCE_TABLE_SIZE, tve); 926 uint32_t tps = GETFIELD(IODA3_TVT_IO_PSIZE, tve); 927 928 /* Invalid levels */ 929 if (lev > 4) { 930 phb_error(ds->phb, "Invalid #levels in TVE %d", lev); 931 return; 932 } 933 934 /* Invalid entry */ 935 if (tts == 0) { 936 phb_error(ds->phb, "Access to invalid TVE"); 937 return; 938 } 939 940 /* IO Page Size of 0 means untranslated, else use TCEs */ 941 if (tps == 0) { 942 /* TODO: Handle boundaries */ 943 944 /* Use 4k pages like q35 ... for now */ 945 tlb->iova = addr & 0xfffffffffffff000ull; 946 tlb->translated_addr = addr & 0x0003fffffffff000ull; 947 tlb->addr_mask = 0xfffull; 948 tlb->perm = IOMMU_RW; 949 } else { 950 uint32_t tce_shift, tbl_shift, sh; 951 uint64_t base, taddr, tce, tce_mask; 952 953 /* Address bits per bottom level TCE entry */ 954 tce_shift = tps + 11; 955 956 /* Address bits per table level */ 957 tbl_shift = tts + 8; 958 959 /* Top level table base address */ 960 base = tta << 12; 961 962 /* Total shift to first level */ 963 sh = tbl_shift * lev + tce_shift; 964 965 /* TODO: Limit to support IO page sizes */ 966 967 /* TODO: Multi-level untested */ 968 while ((lev--) >= 0) { 969 /* Grab the TCE address */ 970 taddr = base | (((addr >> sh) & ((1ul << tbl_shift) - 1)) << 3); 971 if (dma_memory_read(&address_space_memory, taddr, &tce, 972 sizeof(tce), MEMTXATTRS_UNSPECIFIED)) { 973 phb_error(ds->phb, "Failed to read TCE at 0x%"PRIx64, taddr); 974 return; 975 } 976 tce = be64_to_cpu(tce); 977 978 /* Check permission for indirect TCE */ 979 if ((lev >= 0) && !(tce & 3)) { 980 phb_error(ds->phb, "Invalid indirect TCE at 0x%"PRIx64, taddr); 981 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, 982 is_write ? 'W' : 'R', tve); 983 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", 984 tta, lev, tts, tps); 985 return; 986 } 987 sh -= tbl_shift; 988 base = tce & ~0xfffull; 989 } 990 991 /* We exit the loop with TCE being the final TCE */ 992 tce_mask = ~((1ull << tce_shift) - 1); 993 tlb->iova = addr & tce_mask; 994 tlb->translated_addr = tce & tce_mask; 995 tlb->addr_mask = ~tce_mask; 996 tlb->perm = tce & 3; 997 if ((is_write & !(tce & 2)) || ((!is_write) && !(tce & 1))) { 998 phb_error(ds->phb, "TCE access fault at 0x%"PRIx64, taddr); 999 phb_error(ds->phb, " xlate %"PRIx64":%c TVE=%"PRIx64, addr, 1000 is_write ? 'W' : 'R', tve); 1001 phb_error(ds->phb, " tta=%"PRIx64" lev=%d tts=%d tps=%d", 1002 tta, lev, tts, tps); 1003 } 1004 } 1005 } 1006 1007 static IOMMUTLBEntry pnv_phb4_translate_iommu(IOMMUMemoryRegion *iommu, 1008 hwaddr addr, 1009 IOMMUAccessFlags flag, 1010 int iommu_idx) 1011 { 1012 PnvPhb4DMASpace *ds = container_of(iommu, PnvPhb4DMASpace, dma_mr); 1013 int tve_sel; 1014 uint64_t tve, cfg; 1015 IOMMUTLBEntry ret = { 1016 .target_as = &address_space_memory, 1017 .iova = addr, 1018 .translated_addr = 0, 1019 .addr_mask = ~(hwaddr)0, 1020 .perm = IOMMU_NONE, 1021 }; 1022 1023 /* Resolve PE# */ 1024 if (!pnv_phb4_resolve_pe(ds)) { 1025 phb_error(ds->phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x", 1026 ds->bus, pci_bus_num(ds->bus), ds->devfn); 1027 return ret; 1028 } 1029 1030 /* Check top bits */ 1031 switch (addr >> 60) { 1032 case 00: 1033 /* DMA or 32-bit MSI ? */ 1034 cfg = ds->phb->regs[PHB_PHB4_CONFIG >> 3]; 1035 if ((cfg & PHB_PHB4C_32BIT_MSI_EN) && 1036 ((addr & 0xffffffffffff0000ull) == 0xffff0000ull)) { 1037 phb_error(ds->phb, "xlate on 32-bit MSI region"); 1038 return ret; 1039 } 1040 /* Choose TVE XXX Use PHB4 Control Register */ 1041 tve_sel = (addr >> 59) & 1; 1042 tve = ds->phb->ioda_TVT[ds->pe_num * 2 + tve_sel]; 1043 pnv_phb4_translate_tve(ds, addr, flag & IOMMU_WO, tve, &ret); 1044 break; 1045 case 01: 1046 phb_error(ds->phb, "xlate on 64-bit MSI region"); 1047 break; 1048 default: 1049 phb_error(ds->phb, "xlate on unsupported address 0x%"PRIx64, addr); 1050 } 1051 return ret; 1052 } 1053 1054 #define TYPE_PNV_PHB4_IOMMU_MEMORY_REGION "pnv-phb4-iommu-memory-region" 1055 DECLARE_INSTANCE_CHECKER(IOMMUMemoryRegion, PNV_PHB4_IOMMU_MEMORY_REGION, 1056 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION) 1057 1058 static void pnv_phb4_iommu_memory_region_class_init(ObjectClass *klass, 1059 void *data) 1060 { 1061 IOMMUMemoryRegionClass *imrc = IOMMU_MEMORY_REGION_CLASS(klass); 1062 1063 imrc->translate = pnv_phb4_translate_iommu; 1064 } 1065 1066 static const TypeInfo pnv_phb4_iommu_memory_region_info = { 1067 .parent = TYPE_IOMMU_MEMORY_REGION, 1068 .name = TYPE_PNV_PHB4_IOMMU_MEMORY_REGION, 1069 .class_init = pnv_phb4_iommu_memory_region_class_init, 1070 }; 1071 1072 /* 1073 * Return the index/phb-id of a PHB4 that belongs to a 1074 * pec->stacks[stack_index] stack. 1075 */ 1076 int pnv_phb4_pec_get_phb_id(PnvPhb4PecState *pec, int stack_index) 1077 { 1078 PnvPhb4PecClass *pecc = PNV_PHB4_PEC_GET_CLASS(pec); 1079 int index = pec->index; 1080 int offset = 0; 1081 1082 while (index--) { 1083 offset += pecc->num_stacks[index]; 1084 } 1085 1086 return offset + stack_index; 1087 } 1088 1089 /* 1090 * MSI/MSIX memory region implementation. 1091 * The handler handles both MSI and MSIX. 1092 */ 1093 static void pnv_phb4_msi_write(void *opaque, hwaddr addr, 1094 uint64_t data, unsigned size) 1095 { 1096 PnvPhb4DMASpace *ds = opaque; 1097 PnvPHB4 *phb = ds->phb; 1098 1099 uint32_t src = ((addr >> 4) & 0xffff) | (data & 0x1f); 1100 1101 /* Resolve PE# */ 1102 if (!pnv_phb4_resolve_pe(ds)) { 1103 phb_error(phb, "Failed to resolve PE# for bus @%p (%d) devfn 0x%x", 1104 ds->bus, pci_bus_num(ds->bus), ds->devfn); 1105 return; 1106 } 1107 1108 /* TODO: Check it doesn't collide with LSIs */ 1109 if (src >= phb->xsrc.nr_irqs) { 1110 phb_error(phb, "MSI %d out of bounds", src); 1111 return; 1112 } 1113 1114 /* TODO: check PE/MSI assignement */ 1115 1116 qemu_irq_pulse(phb->qirqs[src]); 1117 } 1118 1119 /* There is no .read as the read result is undefined by PCI spec */ 1120 static uint64_t pnv_phb4_msi_read(void *opaque, hwaddr addr, unsigned size) 1121 { 1122 PnvPhb4DMASpace *ds = opaque; 1123 1124 phb_error(ds->phb, "Invalid MSI read @ 0x%" HWADDR_PRIx, addr); 1125 return -1; 1126 } 1127 1128 static const MemoryRegionOps pnv_phb4_msi_ops = { 1129 .read = pnv_phb4_msi_read, 1130 .write = pnv_phb4_msi_write, 1131 .endianness = DEVICE_LITTLE_ENDIAN 1132 }; 1133 1134 static PnvPhb4DMASpace *pnv_phb4_dma_find(PnvPHB4 *phb, PCIBus *bus, int devfn) 1135 { 1136 PnvPhb4DMASpace *ds; 1137 1138 QLIST_FOREACH(ds, &phb->dma_spaces, list) { 1139 if (ds->bus == bus && ds->devfn == devfn) { 1140 break; 1141 } 1142 } 1143 return ds; 1144 } 1145 1146 static AddressSpace *pnv_phb4_dma_iommu(PCIBus *bus, void *opaque, int devfn) 1147 { 1148 PnvPHB4 *phb = opaque; 1149 PnvPhb4DMASpace *ds; 1150 char name[32]; 1151 1152 ds = pnv_phb4_dma_find(phb, bus, devfn); 1153 1154 if (ds == NULL) { 1155 ds = g_malloc0(sizeof(PnvPhb4DMASpace)); 1156 ds->bus = bus; 1157 ds->devfn = devfn; 1158 ds->pe_num = PHB_INVALID_PE; 1159 ds->phb = phb; 1160 snprintf(name, sizeof(name), "phb4-%d.%d-iommu", phb->chip_id, 1161 phb->phb_id); 1162 memory_region_init_iommu(&ds->dma_mr, sizeof(ds->dma_mr), 1163 TYPE_PNV_PHB4_IOMMU_MEMORY_REGION, 1164 OBJECT(phb), name, UINT64_MAX); 1165 address_space_init(&ds->dma_as, MEMORY_REGION(&ds->dma_mr), 1166 name); 1167 memory_region_init_io(&ds->msi32_mr, OBJECT(phb), &pnv_phb4_msi_ops, 1168 ds, "msi32", 0x10000); 1169 memory_region_init_io(&ds->msi64_mr, OBJECT(phb), &pnv_phb4_msi_ops, 1170 ds, "msi64", 0x100000); 1171 pnv_phb4_update_msi_regions(ds); 1172 1173 QLIST_INSERT_HEAD(&phb->dma_spaces, ds, list); 1174 } 1175 return &ds->dma_as; 1176 } 1177 1178 static void pnv_phb4_instance_init(Object *obj) 1179 { 1180 PnvPHB4 *phb = PNV_PHB4(obj); 1181 1182 QLIST_INIT(&phb->dma_spaces); 1183 1184 /* XIVE interrupt source object */ 1185 object_initialize_child(obj, "source", &phb->xsrc, TYPE_XIVE_SOURCE); 1186 } 1187 1188 static void pnv_phb4_realize(DeviceState *dev, Error **errp) 1189 { 1190 PnvPHB4 *phb = PNV_PHB4(dev); 1191 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 1192 XiveSource *xsrc = &phb->xsrc; 1193 int nr_irqs; 1194 char name[32]; 1195 1196 assert(phb->stack); 1197 1198 /* Set the "big_phb" flag */ 1199 phb->big_phb = phb->phb_id == 0 || phb->phb_id == 3; 1200 1201 /* Controller Registers */ 1202 snprintf(name, sizeof(name), "phb4-%d.%d-regs", phb->chip_id, 1203 phb->phb_id); 1204 memory_region_init_io(&phb->mr_regs, OBJECT(phb), &pnv_phb4_reg_ops, phb, 1205 name, 0x2000); 1206 1207 /* 1208 * PHB4 doesn't support IO space. However, qemu gets very upset if 1209 * we don't have an IO region to anchor IO BARs onto so we just 1210 * initialize one which we never hook up to anything 1211 */ 1212 1213 snprintf(name, sizeof(name), "phb4-%d.%d-pci-io", phb->chip_id, 1214 phb->phb_id); 1215 memory_region_init(&phb->pci_io, OBJECT(phb), name, 0x10000); 1216 1217 snprintf(name, sizeof(name), "phb4-%d.%d-pci-mmio", phb->chip_id, 1218 phb->phb_id); 1219 memory_region_init(&phb->pci_mmio, OBJECT(phb), name, 1220 PCI_MMIO_TOTAL_SIZE); 1221 1222 pci->bus = pci_register_root_bus(dev, dev->id, 1223 pnv_phb4_set_irq, pnv_phb4_map_irq, phb, 1224 &phb->pci_mmio, &phb->pci_io, 1225 0, 4, TYPE_PNV_PHB4_ROOT_BUS); 1226 pci_setup_iommu(pci->bus, pnv_phb4_dma_iommu, phb); 1227 pci->bus->flags |= PCI_BUS_EXTENDED_CONFIG_SPACE; 1228 1229 /* Add a single Root port if running with defaults */ 1230 if (defaults_enabled()) { 1231 pnv_phb_attach_root_port(PCI_HOST_BRIDGE(phb), 1232 TYPE_PNV_PHB4_ROOT_PORT); 1233 } 1234 1235 /* Setup XIVE Source */ 1236 if (phb->big_phb) { 1237 nr_irqs = PNV_PHB4_MAX_INTs; 1238 } else { 1239 nr_irqs = PNV_PHB4_MAX_INTs >> 1; 1240 } 1241 object_property_set_int(OBJECT(xsrc), "nr-irqs", nr_irqs, &error_fatal); 1242 object_property_set_link(OBJECT(xsrc), "xive", OBJECT(phb), &error_fatal); 1243 if (!qdev_realize(DEVICE(xsrc), NULL, errp)) { 1244 return; 1245 } 1246 1247 pnv_phb4_update_xsrc(phb); 1248 1249 phb->qirqs = qemu_allocate_irqs(xive_source_set_irq, xsrc, xsrc->nr_irqs); 1250 } 1251 1252 static const char *pnv_phb4_root_bus_path(PCIHostState *host_bridge, 1253 PCIBus *rootbus) 1254 { 1255 PnvPHB4 *phb = PNV_PHB4(host_bridge); 1256 1257 snprintf(phb->bus_path, sizeof(phb->bus_path), "00%02x:%02x", 1258 phb->chip_id, phb->phb_id); 1259 return phb->bus_path; 1260 } 1261 1262 static void pnv_phb4_xive_notify(XiveNotifier *xf, uint32_t srcno) 1263 { 1264 PnvPHB4 *phb = PNV_PHB4(xf); 1265 uint64_t notif_port = phb->regs[PHB_INT_NOTIFY_ADDR >> 3]; 1266 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; 1267 uint64_t data = XIVE_TRIGGER_PQ | offset | srcno; 1268 MemTxResult result; 1269 1270 trace_pnv_phb4_xive_notify(notif_port, data); 1271 1272 address_space_stq_be(&address_space_memory, notif_port, data, 1273 MEMTXATTRS_UNSPECIFIED, &result); 1274 if (result != MEMTX_OK) { 1275 phb_error(phb, "trigger failed @%"HWADDR_PRIx "\n", notif_port); 1276 return; 1277 } 1278 } 1279 1280 static Property pnv_phb4_properties[] = { 1281 DEFINE_PROP_UINT32("index", PnvPHB4, phb_id, 0), 1282 DEFINE_PROP_UINT32("chip-id", PnvPHB4, chip_id, 0), 1283 DEFINE_PROP_UINT64("version", PnvPHB4, version, 0), 1284 DEFINE_PROP_LINK("stack", PnvPHB4, stack, TYPE_PNV_PHB4_PEC_STACK, 1285 PnvPhb4PecStack *), 1286 DEFINE_PROP_END_OF_LIST(), 1287 }; 1288 1289 static void pnv_phb4_class_init(ObjectClass *klass, void *data) 1290 { 1291 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 1292 DeviceClass *dc = DEVICE_CLASS(klass); 1293 XiveNotifierClass *xfc = XIVE_NOTIFIER_CLASS(klass); 1294 1295 hc->root_bus_path = pnv_phb4_root_bus_path; 1296 dc->realize = pnv_phb4_realize; 1297 device_class_set_props(dc, pnv_phb4_properties); 1298 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 1299 dc->user_creatable = false; 1300 1301 xfc->notify = pnv_phb4_xive_notify; 1302 } 1303 1304 static const TypeInfo pnv_phb4_type_info = { 1305 .name = TYPE_PNV_PHB4, 1306 .parent = TYPE_PCIE_HOST_BRIDGE, 1307 .instance_init = pnv_phb4_instance_init, 1308 .instance_size = sizeof(PnvPHB4), 1309 .class_init = pnv_phb4_class_init, 1310 .interfaces = (InterfaceInfo[]) { 1311 { TYPE_XIVE_NOTIFIER }, 1312 { }, 1313 } 1314 }; 1315 1316 static void pnv_phb4_root_bus_class_init(ObjectClass *klass, void *data) 1317 { 1318 BusClass *k = BUS_CLASS(klass); 1319 1320 /* 1321 * PHB4 has only a single root complex. Enforce the limit on the 1322 * parent bus 1323 */ 1324 k->max_dev = 1; 1325 } 1326 1327 static const TypeInfo pnv_phb4_root_bus_info = { 1328 .name = TYPE_PNV_PHB4_ROOT_BUS, 1329 .parent = TYPE_PCIE_BUS, 1330 .class_init = pnv_phb4_root_bus_class_init, 1331 .interfaces = (InterfaceInfo[]) { 1332 { INTERFACE_PCIE_DEVICE }, 1333 { } 1334 }, 1335 }; 1336 1337 static void pnv_phb4_root_port_reset(DeviceState *dev) 1338 { 1339 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 1340 PCIDevice *d = PCI_DEVICE(dev); 1341 uint8_t *conf = d->config; 1342 1343 rpc->parent_reset(dev); 1344 1345 pci_byte_test_and_set_mask(conf + PCI_IO_BASE, 1346 PCI_IO_RANGE_MASK & 0xff); 1347 pci_byte_test_and_clear_mask(conf + PCI_IO_LIMIT, 1348 PCI_IO_RANGE_MASK & 0xff); 1349 pci_set_word(conf + PCI_MEMORY_BASE, 0); 1350 pci_set_word(conf + PCI_MEMORY_LIMIT, 0xfff0); 1351 pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0x1); 1352 pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0xfff1); 1353 pci_set_long(conf + PCI_PREF_BASE_UPPER32, 0x1); /* Hack */ 1354 pci_set_long(conf + PCI_PREF_LIMIT_UPPER32, 0xffffffff); 1355 } 1356 1357 static void pnv_phb4_root_port_realize(DeviceState *dev, Error **errp) 1358 { 1359 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev); 1360 PCIDevice *pci = PCI_DEVICE(dev); 1361 PCIBus *bus = pci_get_bus(pci); 1362 PnvPHB4 *phb = NULL; 1363 Error *local_err = NULL; 1364 1365 phb = (PnvPHB4 *) object_dynamic_cast(OBJECT(bus->qbus.parent), 1366 TYPE_PNV_PHB4); 1367 1368 if (!phb) { 1369 error_setg(errp, "%s must be connected to pnv-phb4 buses", dev->id); 1370 return; 1371 } 1372 1373 /* Set unique chassis/slot values for the root port */ 1374 qdev_prop_set_uint8(&pci->qdev, "chassis", phb->chip_id); 1375 qdev_prop_set_uint16(&pci->qdev, "slot", phb->phb_id); 1376 1377 rpc->parent_realize(dev, &local_err); 1378 if (local_err) { 1379 error_propagate(errp, local_err); 1380 return; 1381 } 1382 } 1383 1384 static void pnv_phb4_root_port_class_init(ObjectClass *klass, void *data) 1385 { 1386 DeviceClass *dc = DEVICE_CLASS(klass); 1387 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 1388 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); 1389 1390 dc->desc = "IBM PHB4 PCIE Root Port"; 1391 dc->user_creatable = true; 1392 1393 device_class_set_parent_realize(dc, pnv_phb4_root_port_realize, 1394 &rpc->parent_realize); 1395 device_class_set_parent_reset(dc, pnv_phb4_root_port_reset, 1396 &rpc->parent_reset); 1397 1398 k->vendor_id = PCI_VENDOR_ID_IBM; 1399 k->device_id = PNV_PHB4_DEVICE_ID; 1400 k->revision = 0; 1401 1402 rpc->exp_offset = 0x48; 1403 rpc->aer_offset = 0x100; 1404 1405 dc->reset = &pnv_phb4_root_port_reset; 1406 } 1407 1408 static const TypeInfo pnv_phb4_root_port_info = { 1409 .name = TYPE_PNV_PHB4_ROOT_PORT, 1410 .parent = TYPE_PCIE_ROOT_PORT, 1411 .instance_size = sizeof(PnvPHB4RootPort), 1412 .class_init = pnv_phb4_root_port_class_init, 1413 }; 1414 1415 static void pnv_phb4_register_types(void) 1416 { 1417 type_register_static(&pnv_phb4_root_bus_info); 1418 type_register_static(&pnv_phb4_root_port_info); 1419 type_register_static(&pnv_phb4_type_info); 1420 type_register_static(&pnv_phb4_iommu_memory_region_info); 1421 } 1422 1423 type_init(pnv_phb4_register_types); 1424 1425 void pnv_phb4_update_regions(PnvPhb4PecStack *stack) 1426 { 1427 PnvPHB4 *phb = &stack->phb; 1428 1429 /* Unmap first always */ 1430 if (memory_region_is_mapped(&phb->mr_regs)) { 1431 memory_region_del_subregion(&stack->phbbar, &phb->mr_regs); 1432 } 1433 if (memory_region_is_mapped(&phb->xsrc.esb_mmio)) { 1434 memory_region_del_subregion(&stack->intbar, &phb->xsrc.esb_mmio); 1435 } 1436 1437 /* Map registers if enabled */ 1438 if (memory_region_is_mapped(&stack->phbbar)) { 1439 memory_region_add_subregion(&stack->phbbar, 0, &phb->mr_regs); 1440 } 1441 1442 /* Map ESB if enabled */ 1443 if (memory_region_is_mapped(&stack->intbar)) { 1444 memory_region_add_subregion(&stack->intbar, 0, &phb->xsrc.esb_mmio); 1445 } 1446 1447 /* Check/update m32 */ 1448 pnv_phb4_check_all_mbt(phb); 1449 } 1450 1451 void pnv_phb4_pic_print_info(PnvPHB4 *phb, Monitor *mon) 1452 { 1453 uint32_t offset = phb->regs[PHB_INT_NOTIFY_INDEX >> 3]; 1454 1455 monitor_printf(mon, "PHB4[%x:%x] Source %08x .. %08x\n", 1456 phb->chip_id, phb->phb_id, 1457 offset, offset + phb->xsrc.nr_irqs - 1); 1458 xive_source_pic_print_info(&phb->xsrc, 0, mon); 1459 } 1460