1 /* 2 * QEMU i440FX PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/range.h" 28 #include "hw/i386/pc.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_host.h" 31 #include "hw/pci-host/i440fx.h" 32 #include "hw/qdev-properties.h" 33 #include "hw/sysbus.h" 34 #include "qapi/error.h" 35 #include "migration/vmstate.h" 36 #include "qapi/visitor.h" 37 #include "qemu/error-report.h" 38 #include "qom/object.h" 39 40 /* 41 * I440FX chipset data sheet. 42 * https://wiki.qemu.org/File:29054901.pdf 43 */ 44 45 OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE) 46 47 struct I440FXState { 48 PCIHostState parent_obj; 49 50 MemoryRegion *system_memory; 51 MemoryRegion *io_memory; 52 MemoryRegion *pci_address_space; 53 MemoryRegion *ram_memory; 54 Range pci_hole; 55 uint64_t below_4g_mem_size; 56 uint64_t above_4g_mem_size; 57 uint64_t pci_hole64_size; 58 bool pci_hole64_fix; 59 uint32_t short_root_bus; 60 61 char *pci_type; 62 }; 63 64 #define I440FX_PAM 0x59 65 #define I440FX_PAM_SIZE 7 66 #define I440FX_SMRAM 0x72 67 68 /* Keep it 2G to comply with older win32 guests */ 69 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31) 70 71 /* Older coreboot versions (4.0 and older) read a config register that doesn't 72 * exist in real hardware, to get the RAM size from QEMU. 73 */ 74 #define I440FX_COREBOOT_RAM_SIZE 0x57 75 76 static void i440fx_realize(PCIDevice *dev, Error **errp) 77 { 78 dev->config[I440FX_SMRAM] = 0x02; 79 80 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { 81 warn_report("i440fx doesn't support emulated iommu"); 82 } 83 } 84 85 static void i440fx_update_memory_mappings(PCII440FXState *d) 86 { 87 int i; 88 PCIDevice *pd = PCI_DEVICE(d); 89 90 memory_region_transaction_begin(); 91 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { 92 pam_update(&d->pam_regions[i], i, 93 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); 94 } 95 memory_region_set_enabled(&d->smram_region, 96 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); 97 memory_region_set_enabled(&d->smram, 98 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME); 99 memory_region_transaction_commit(); 100 } 101 102 103 static void i440fx_write_config(PCIDevice *dev, 104 uint32_t address, uint32_t val, int len) 105 { 106 PCII440FXState *d = I440FX_PCI_DEVICE(dev); 107 108 /* XXX: implement SMRAM.D_LOCK */ 109 pci_default_write_config(dev, address, val, len); 110 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || 111 range_covers_byte(address, len, I440FX_SMRAM)) { 112 i440fx_update_memory_mappings(d); 113 } 114 } 115 116 static int i440fx_post_load(void *opaque, int version_id) 117 { 118 PCII440FXState *d = opaque; 119 120 i440fx_update_memory_mappings(d); 121 return 0; 122 } 123 124 static const VMStateDescription vmstate_i440fx = { 125 .name = "I440FX", 126 .version_id = 3, 127 .minimum_version_id = 3, 128 .post_load = i440fx_post_load, 129 .fields = (VMStateField[]) { 130 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), 131 /* Used to be smm_enabled, which was basically always zero because 132 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 133 */ 134 VMSTATE_UNUSED(1), 135 VMSTATE_END_OF_LIST() 136 } 137 }; 138 139 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v, 140 const char *name, void *opaque, 141 Error **errp) 142 { 143 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 144 uint64_t val64; 145 uint32_t value; 146 147 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); 148 value = val64; 149 assert(value == val64); 150 visit_type_uint32(v, name, &value, errp); 151 } 152 153 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v, 154 const char *name, void *opaque, 155 Error **errp) 156 { 157 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 158 uint64_t val64; 159 uint32_t value; 160 161 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; 162 value = val64; 163 assert(value == val64); 164 visit_type_uint32(v, name, &value, errp); 165 } 166 167 /* 168 * The 64bit PCI hole start is set by the Guest firmware 169 * as the address of the first 64bit PCI MEM resource. 170 * If no PCI device has resources on the 64bit area, 171 * the 64bit PCI hole will start after "over 4G RAM" and the 172 * reserved space for memory hotplug if any. 173 */ 174 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj) 175 { 176 PCIHostState *h = PCI_HOST_BRIDGE(obj); 177 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 178 Range w64; 179 uint64_t value; 180 181 pci_bus_get_w64_range(h->bus, &w64); 182 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 183 if (!value && s->pci_hole64_fix) { 184 value = pc_pci_hole64_start(); 185 } 186 return value; 187 } 188 189 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, 190 const char *name, 191 void *opaque, Error **errp) 192 { 193 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); 194 195 visit_type_uint64(v, name, &hole64_start, errp); 196 } 197 198 /* 199 * The 64bit PCI hole end is set by the Guest firmware 200 * as the address of the last 64bit PCI MEM resource. 201 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 202 * that can be configured by the user. 203 */ 204 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, 205 const char *name, void *opaque, 206 Error **errp) 207 { 208 PCIHostState *h = PCI_HOST_BRIDGE(obj); 209 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 210 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); 211 Range w64; 212 uint64_t value, hole64_end; 213 214 pci_bus_get_w64_range(h->bus, &w64); 215 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 216 hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30); 217 if (s->pci_hole64_fix && value < hole64_end) { 218 value = hole64_end; 219 } 220 visit_type_uint64(v, name, &value, errp); 221 } 222 223 static void i440fx_pcihost_initfn(Object *obj) 224 { 225 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 226 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 227 228 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, phb, 229 "pci-conf-idx", 4); 230 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, phb, 231 "pci-conf-data", 4); 232 233 object_property_add_link(obj, PCI_HOST_PROP_RAM_MEM, TYPE_MEMORY_REGION, 234 (Object **) &s->ram_memory, 235 qdev_prop_allow_set_link_before_realize, 0); 236 237 object_property_add_link(obj, PCI_HOST_PROP_PCI_MEM, TYPE_MEMORY_REGION, 238 (Object **) &s->pci_address_space, 239 qdev_prop_allow_set_link_before_realize, 0); 240 241 object_property_add_link(obj, PCI_HOST_PROP_SYSTEM_MEM, TYPE_MEMORY_REGION, 242 (Object **) &s->system_memory, 243 qdev_prop_allow_set_link_before_realize, 0); 244 245 object_property_add_link(obj, PCI_HOST_PROP_IO_MEM, TYPE_MEMORY_REGION, 246 (Object **) &s->io_memory, 247 qdev_prop_allow_set_link_before_realize, 0); 248 } 249 250 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) 251 { 252 ERRP_GUARD(); 253 I440FXState *s = I440FX_PCI_HOST_BRIDGE(dev); 254 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 255 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 256 PCIBus *b; 257 PCIDevice *d; 258 PCII440FXState *f; 259 unsigned i; 260 261 memory_region_add_subregion(s->io_memory, 0xcf8, &phb->conf_mem); 262 sysbus_init_ioports(sbd, 0xcf8, 4); 263 264 memory_region_add_subregion(s->io_memory, 0xcfc, &phb->data_mem); 265 sysbus_init_ioports(sbd, 0xcfc, 4); 266 267 /* register i440fx 0xcf8 port as coalesced pio */ 268 memory_region_set_flush_coalesced(&phb->data_mem); 269 memory_region_add_coalescing(&phb->conf_mem, 0, 4); 270 271 b = pci_root_bus_new(dev, NULL, s->pci_address_space, 272 s->io_memory, 0, TYPE_PCI_BUS); 273 phb->bus = b; 274 275 d = pci_create_simple(b, 0, s->pci_type); 276 f = I440FX_PCI_DEVICE(d); 277 278 range_set_bounds(&s->pci_hole, s->below_4g_mem_size, 279 IO_APIC_DEFAULT_ADDRESS - 1); 280 281 /* setup pci memory mapping */ 282 pc_pci_as_mapping_init(s->system_memory, s->pci_address_space); 283 284 /* if *disabled* show SMRAM to all CPUs */ 285 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", 286 s->pci_address_space, SMRAM_C_BASE, SMRAM_C_SIZE); 287 memory_region_add_subregion_overlap(s->system_memory, SMRAM_C_BASE, 288 &f->smram_region, 1); 289 memory_region_set_enabled(&f->smram_region, true); 290 291 /* smram, as seen by SMM CPUs */ 292 memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB); 293 memory_region_set_enabled(&f->smram, true); 294 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", 295 s->ram_memory, SMRAM_C_BASE, SMRAM_C_SIZE); 296 memory_region_set_enabled(&f->low_smram, true); 297 memory_region_add_subregion(&f->smram, SMRAM_C_BASE, &f->low_smram); 298 object_property_add_const_link(qdev_get_machine(), "smram", 299 OBJECT(&f->smram)); 300 301 init_pam(&f->pam_regions[0], OBJECT(d), s->ram_memory, s->system_memory, 302 s->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE); 303 for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) { 304 init_pam(&f->pam_regions[i + 1], OBJECT(d), s->ram_memory, 305 s->system_memory, s->pci_address_space, 306 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 307 } 308 309 ram_addr_t ram_size = s->below_4g_mem_size + s->above_4g_mem_size; 310 ram_size = ram_size / 8 / 1024 / 1024; 311 if (ram_size > 255) { 312 ram_size = 255; 313 } 314 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; 315 316 i440fx_update_memory_mappings(f); 317 } 318 319 static void i440fx_class_init(ObjectClass *klass, void *data) 320 { 321 DeviceClass *dc = DEVICE_CLASS(klass); 322 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 323 324 k->realize = i440fx_realize; 325 k->config_write = i440fx_write_config; 326 k->vendor_id = PCI_VENDOR_ID_INTEL; 327 k->device_id = PCI_DEVICE_ID_INTEL_82441; 328 k->revision = 0x02; 329 k->class_id = PCI_CLASS_BRIDGE_HOST; 330 dc->desc = "Host bridge"; 331 dc->vmsd = &vmstate_i440fx; 332 /* 333 * PCI-facing part of the host bridge, not usable without the 334 * host-facing part, which can't be device_add'ed, yet. 335 */ 336 dc->user_creatable = false; 337 dc->hotpluggable = false; 338 } 339 340 static const TypeInfo i440fx_info = { 341 .name = TYPE_I440FX_PCI_DEVICE, 342 .parent = TYPE_PCI_DEVICE, 343 .instance_size = sizeof(PCII440FXState), 344 .class_init = i440fx_class_init, 345 .interfaces = (InterfaceInfo[]) { 346 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 347 { }, 348 }, 349 }; 350 351 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, 352 PCIBus *rootbus) 353 { 354 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge); 355 356 /* For backwards compat with old device paths */ 357 if (s->short_root_bus) { 358 return "0000"; 359 } 360 return "0000:00"; 361 } 362 363 static Property i440fx_props[] = { 364 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, 365 pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT), 366 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0), 367 DEFINE_PROP_SIZE(PCI_HOST_BELOW_4G_MEM_SIZE, I440FXState, 368 below_4g_mem_size, 0), 369 DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MEM_SIZE, I440FXState, 370 above_4g_mem_size, 0), 371 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), 372 DEFINE_PROP_STRING(I440FX_HOST_PROP_PCI_TYPE, I440FXState, pci_type), 373 DEFINE_PROP_END_OF_LIST(), 374 }; 375 376 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) 377 { 378 DeviceClass *dc = DEVICE_CLASS(klass); 379 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 380 381 hc->root_bus_path = i440fx_pcihost_root_bus_path; 382 dc->realize = i440fx_pcihost_realize; 383 dc->fw_name = "pci"; 384 device_class_set_props(dc, i440fx_props); 385 /* Reason: needs to be wired up by pc_init1 */ 386 dc->user_creatable = false; 387 388 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 389 i440fx_pcihost_get_pci_hole_start, 390 NULL, NULL, NULL); 391 392 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 393 i440fx_pcihost_get_pci_hole_end, 394 NULL, NULL, NULL); 395 396 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 397 i440fx_pcihost_get_pci_hole64_start, 398 NULL, NULL, NULL); 399 400 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 401 i440fx_pcihost_get_pci_hole64_end, 402 NULL, NULL, NULL); 403 } 404 405 static const TypeInfo i440fx_pcihost_info = { 406 .name = TYPE_I440FX_PCI_HOST_BRIDGE, 407 .parent = TYPE_PCI_HOST_BRIDGE, 408 .instance_size = sizeof(I440FXState), 409 .instance_init = i440fx_pcihost_initfn, 410 .class_init = i440fx_pcihost_class_init, 411 }; 412 413 static void i440fx_register_types(void) 414 { 415 type_register_static(&i440fx_info); 416 type_register_static(&i440fx_pcihost_info); 417 } 418 419 type_init(i440fx_register_types) 420