1 /* 2 * QEMU i440FX PCI Bridge Emulation 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a copy 7 * of this software and associated documentation files (the "Software"), to deal 8 * in the Software without restriction, including without limitation the rights 9 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 10 * copies of the Software, and to permit persons to whom the Software is 11 * furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 21 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 22 * THE SOFTWARE. 23 */ 24 25 #include "qemu/osdep.h" 26 #include "qemu/units.h" 27 #include "qemu/range.h" 28 #include "hw/i386/pc.h" 29 #include "hw/pci/pci.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci/pci_host.h" 32 #include "hw/pci-host/i440fx.h" 33 #include "hw/qdev-properties.h" 34 #include "hw/sysbus.h" 35 #include "qapi/error.h" 36 #include "migration/vmstate.h" 37 #include "qapi/visitor.h" 38 #include "qemu/error-report.h" 39 #include "qom/object.h" 40 41 /* 42 * I440FX chipset data sheet. 43 * https://wiki.qemu.org/File:29054901.pdf 44 */ 45 46 OBJECT_DECLARE_SIMPLE_TYPE(I440FXState, I440FX_PCI_HOST_BRIDGE) 47 48 struct I440FXState { 49 PCIHostState parent_obj; 50 Range pci_hole; 51 uint64_t pci_hole64_size; 52 bool pci_hole64_fix; 53 uint32_t short_root_bus; 54 }; 55 56 #define I440FX_PAM 0x59 57 #define I440FX_PAM_SIZE 7 58 #define I440FX_SMRAM 0x72 59 60 /* Keep it 2G to comply with older win32 guests */ 61 #define I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT (1ULL << 31) 62 63 /* Older coreboot versions (4.0 and older) read a config register that doesn't 64 * exist in real hardware, to get the RAM size from QEMU. 65 */ 66 #define I440FX_COREBOOT_RAM_SIZE 0x57 67 68 static void i440fx_update_memory_mappings(PCII440FXState *d) 69 { 70 int i; 71 PCIDevice *pd = PCI_DEVICE(d); 72 73 memory_region_transaction_begin(); 74 for (i = 0; i < ARRAY_SIZE(d->pam_regions); i++) { 75 pam_update(&d->pam_regions[i], i, 76 pd->config[I440FX_PAM + DIV_ROUND_UP(i, 2)]); 77 } 78 memory_region_set_enabled(&d->smram_region, 79 !(pd->config[I440FX_SMRAM] & SMRAM_D_OPEN)); 80 memory_region_set_enabled(&d->smram, 81 pd->config[I440FX_SMRAM] & SMRAM_G_SMRAME); 82 memory_region_transaction_commit(); 83 } 84 85 86 static void i440fx_write_config(PCIDevice *dev, 87 uint32_t address, uint32_t val, int len) 88 { 89 PCII440FXState *d = I440FX_PCI_DEVICE(dev); 90 91 /* XXX: implement SMRAM.D_LOCK */ 92 pci_default_write_config(dev, address, val, len); 93 if (ranges_overlap(address, len, I440FX_PAM, I440FX_PAM_SIZE) || 94 range_covers_byte(address, len, I440FX_SMRAM)) { 95 i440fx_update_memory_mappings(d); 96 } 97 } 98 99 static int i440fx_post_load(void *opaque, int version_id) 100 { 101 PCII440FXState *d = opaque; 102 103 i440fx_update_memory_mappings(d); 104 return 0; 105 } 106 107 static const VMStateDescription vmstate_i440fx = { 108 .name = "I440FX", 109 .version_id = 3, 110 .minimum_version_id = 3, 111 .post_load = i440fx_post_load, 112 .fields = (VMStateField[]) { 113 VMSTATE_PCI_DEVICE(parent_obj, PCII440FXState), 114 /* Used to be smm_enabled, which was basically always zero because 115 * SeaBIOS hardly uses SMM. SMRAM is now handled by CPU code. 116 */ 117 VMSTATE_UNUSED(1), 118 VMSTATE_END_OF_LIST() 119 } 120 }; 121 122 static void i440fx_pcihost_get_pci_hole_start(Object *obj, Visitor *v, 123 const char *name, void *opaque, 124 Error **errp) 125 { 126 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 127 uint64_t val64; 128 uint32_t value; 129 130 val64 = range_is_empty(&s->pci_hole) ? 0 : range_lob(&s->pci_hole); 131 value = val64; 132 assert(value == val64); 133 visit_type_uint32(v, name, &value, errp); 134 } 135 136 static void i440fx_pcihost_get_pci_hole_end(Object *obj, Visitor *v, 137 const char *name, void *opaque, 138 Error **errp) 139 { 140 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 141 uint64_t val64; 142 uint32_t value; 143 144 val64 = range_is_empty(&s->pci_hole) ? 0 : range_upb(&s->pci_hole) + 1; 145 value = val64; 146 assert(value == val64); 147 visit_type_uint32(v, name, &value, errp); 148 } 149 150 /* 151 * The 64bit PCI hole start is set by the Guest firmware 152 * as the address of the first 64bit PCI MEM resource. 153 * If no PCI device has resources on the 64bit area, 154 * the 64bit PCI hole will start after "over 4G RAM" and the 155 * reserved space for memory hotplug if any. 156 */ 157 static uint64_t i440fx_pcihost_get_pci_hole64_start_value(Object *obj) 158 { 159 PCIHostState *h = PCI_HOST_BRIDGE(obj); 160 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 161 Range w64; 162 uint64_t value; 163 164 pci_bus_get_w64_range(h->bus, &w64); 165 value = range_is_empty(&w64) ? 0 : range_lob(&w64); 166 if (!value && s->pci_hole64_fix) { 167 value = pc_pci_hole64_start(); 168 } 169 return value; 170 } 171 172 static void i440fx_pcihost_get_pci_hole64_start(Object *obj, Visitor *v, 173 const char *name, 174 void *opaque, Error **errp) 175 { 176 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); 177 178 visit_type_uint64(v, name, &hole64_start, errp); 179 } 180 181 /* 182 * The 64bit PCI hole end is set by the Guest firmware 183 * as the address of the last 64bit PCI MEM resource. 184 * Then it is expanded to the PCI_HOST_PROP_PCI_HOLE64_SIZE 185 * that can be configured by the user. 186 */ 187 static void i440fx_pcihost_get_pci_hole64_end(Object *obj, Visitor *v, 188 const char *name, void *opaque, 189 Error **errp) 190 { 191 PCIHostState *h = PCI_HOST_BRIDGE(obj); 192 I440FXState *s = I440FX_PCI_HOST_BRIDGE(obj); 193 uint64_t hole64_start = i440fx_pcihost_get_pci_hole64_start_value(obj); 194 Range w64; 195 uint64_t value, hole64_end; 196 197 pci_bus_get_w64_range(h->bus, &w64); 198 value = range_is_empty(&w64) ? 0 : range_upb(&w64) + 1; 199 hole64_end = ROUND_UP(hole64_start + s->pci_hole64_size, 1ULL << 30); 200 if (s->pci_hole64_fix && value < hole64_end) { 201 value = hole64_end; 202 } 203 visit_type_uint64(v, name, &value, errp); 204 } 205 206 static void i440fx_pcihost_initfn(Object *obj) 207 { 208 PCIHostState *s = PCI_HOST_BRIDGE(obj); 209 210 memory_region_init_io(&s->conf_mem, obj, &pci_host_conf_le_ops, s, 211 "pci-conf-idx", 4); 212 memory_region_init_io(&s->data_mem, obj, &pci_host_data_le_ops, s, 213 "pci-conf-data", 4); 214 } 215 216 static void i440fx_pcihost_realize(DeviceState *dev, Error **errp) 217 { 218 PCIHostState *s = PCI_HOST_BRIDGE(dev); 219 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 220 221 memory_region_add_subregion(s->bus->address_space_io, 0xcf8, &s->conf_mem); 222 sysbus_init_ioports(sbd, 0xcf8, 4); 223 224 memory_region_add_subregion(s->bus->address_space_io, 0xcfc, &s->data_mem); 225 sysbus_init_ioports(sbd, 0xcfc, 4); 226 227 /* register i440fx 0xcf8 port as coalesced pio */ 228 memory_region_set_flush_coalesced(&s->data_mem); 229 memory_region_add_coalescing(&s->conf_mem, 0, 4); 230 } 231 232 static void i440fx_realize(PCIDevice *dev, Error **errp) 233 { 234 dev->config[I440FX_SMRAM] = 0x02; 235 236 if (object_property_get_bool(qdev_get_machine(), "iommu", NULL)) { 237 warn_report("i440fx doesn't support emulated iommu"); 238 } 239 } 240 241 PCIBus *i440fx_init(const char *pci_type, 242 DeviceState *dev, 243 MemoryRegion *address_space_mem, 244 MemoryRegion *address_space_io, 245 ram_addr_t ram_size, 246 ram_addr_t below_4g_mem_size, 247 ram_addr_t above_4g_mem_size, 248 MemoryRegion *pci_address_space, 249 MemoryRegion *ram_memory) 250 { 251 PCIBus *b; 252 PCIDevice *d; 253 PCIHostState *s; 254 PCII440FXState *f; 255 unsigned i; 256 I440FXState *i440fx; 257 258 s = PCI_HOST_BRIDGE(dev); 259 b = pci_root_bus_new(dev, NULL, pci_address_space, 260 address_space_io, 0, TYPE_PCI_BUS); 261 s->bus = b; 262 object_property_add_child(qdev_get_machine(), "i440fx", OBJECT(dev)); 263 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 264 265 d = pci_create_simple(b, 0, pci_type); 266 f = I440FX_PCI_DEVICE(d); 267 f->system_memory = address_space_mem; 268 f->pci_address_space = pci_address_space; 269 f->ram_memory = ram_memory; 270 271 i440fx = I440FX_PCI_HOST_BRIDGE(dev); 272 range_set_bounds(&i440fx->pci_hole, below_4g_mem_size, 273 IO_APIC_DEFAULT_ADDRESS - 1); 274 275 /* setup pci memory mapping */ 276 pc_pci_as_mapping_init(f->system_memory, f->pci_address_space); 277 278 /* if *disabled* show SMRAM to all CPUs */ 279 memory_region_init_alias(&f->smram_region, OBJECT(d), "smram-region", 280 f->pci_address_space, 0xa0000, 0x20000); 281 memory_region_add_subregion_overlap(f->system_memory, 0xa0000, 282 &f->smram_region, 1); 283 memory_region_set_enabled(&f->smram_region, true); 284 285 /* smram, as seen by SMM CPUs */ 286 memory_region_init(&f->smram, OBJECT(d), "smram", 4 * GiB); 287 memory_region_set_enabled(&f->smram, true); 288 memory_region_init_alias(&f->low_smram, OBJECT(d), "smram-low", 289 f->ram_memory, 0xa0000, 0x20000); 290 memory_region_set_enabled(&f->low_smram, true); 291 memory_region_add_subregion(&f->smram, 0xa0000, &f->low_smram); 292 object_property_add_const_link(qdev_get_machine(), "smram", 293 OBJECT(&f->smram)); 294 295 init_pam(&f->pam_regions[0], OBJECT(d), f->ram_memory, f->system_memory, 296 f->pci_address_space, PAM_BIOS_BASE, PAM_BIOS_SIZE); 297 for (i = 0; i < ARRAY_SIZE(f->pam_regions) - 1; ++i) { 298 init_pam(&f->pam_regions[i + 1], OBJECT(d), f->ram_memory, 299 f->system_memory, f->pci_address_space, 300 PAM_EXPAN_BASE + i * PAM_EXPAN_SIZE, PAM_EXPAN_SIZE); 301 } 302 303 ram_size = ram_size / 8 / 1024 / 1024; 304 if (ram_size > 255) { 305 ram_size = 255; 306 } 307 d->config[I440FX_COREBOOT_RAM_SIZE] = ram_size; 308 309 i440fx_update_memory_mappings(f); 310 311 return b; 312 } 313 314 static void i440fx_class_init(ObjectClass *klass, void *data) 315 { 316 DeviceClass *dc = DEVICE_CLASS(klass); 317 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 318 319 k->realize = i440fx_realize; 320 k->config_write = i440fx_write_config; 321 k->vendor_id = PCI_VENDOR_ID_INTEL; 322 k->device_id = PCI_DEVICE_ID_INTEL_82441; 323 k->revision = 0x02; 324 k->class_id = PCI_CLASS_BRIDGE_HOST; 325 dc->desc = "Host bridge"; 326 dc->vmsd = &vmstate_i440fx; 327 /* 328 * PCI-facing part of the host bridge, not usable without the 329 * host-facing part, which can't be device_add'ed, yet. 330 */ 331 dc->user_creatable = false; 332 dc->hotpluggable = false; 333 } 334 335 static const TypeInfo i440fx_info = { 336 .name = TYPE_I440FX_PCI_DEVICE, 337 .parent = TYPE_PCI_DEVICE, 338 .instance_size = sizeof(PCII440FXState), 339 .class_init = i440fx_class_init, 340 .interfaces = (InterfaceInfo[]) { 341 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 342 { }, 343 }, 344 }; 345 346 static const char *i440fx_pcihost_root_bus_path(PCIHostState *host_bridge, 347 PCIBus *rootbus) 348 { 349 I440FXState *s = I440FX_PCI_HOST_BRIDGE(host_bridge); 350 351 /* For backwards compat with old device paths */ 352 if (s->short_root_bus) { 353 return "0000"; 354 } 355 return "0000:00"; 356 } 357 358 static Property i440fx_props[] = { 359 DEFINE_PROP_SIZE(PCI_HOST_PROP_PCI_HOLE64_SIZE, I440FXState, 360 pci_hole64_size, I440FX_PCI_HOST_HOLE64_SIZE_DEFAULT), 361 DEFINE_PROP_UINT32("short_root_bus", I440FXState, short_root_bus, 0), 362 DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), 363 DEFINE_PROP_END_OF_LIST(), 364 }; 365 366 static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) 367 { 368 DeviceClass *dc = DEVICE_CLASS(klass); 369 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 370 371 hc->root_bus_path = i440fx_pcihost_root_bus_path; 372 dc->realize = i440fx_pcihost_realize; 373 dc->fw_name = "pci"; 374 device_class_set_props(dc, i440fx_props); 375 /* Reason: needs to be wired up by pc_init1 */ 376 dc->user_creatable = false; 377 378 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_START, "uint32", 379 i440fx_pcihost_get_pci_hole_start, 380 NULL, NULL, NULL); 381 382 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE_END, "uint32", 383 i440fx_pcihost_get_pci_hole_end, 384 NULL, NULL, NULL); 385 386 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_START, "uint64", 387 i440fx_pcihost_get_pci_hole64_start, 388 NULL, NULL, NULL); 389 390 object_class_property_add(klass, PCI_HOST_PROP_PCI_HOLE64_END, "uint64", 391 i440fx_pcihost_get_pci_hole64_end, 392 NULL, NULL, NULL); 393 } 394 395 static const TypeInfo i440fx_pcihost_info = { 396 .name = TYPE_I440FX_PCI_HOST_BRIDGE, 397 .parent = TYPE_PCI_HOST_BRIDGE, 398 .instance_size = sizeof(I440FXState), 399 .instance_init = i440fx_pcihost_initfn, 400 .class_init = i440fx_pcihost_class_init, 401 }; 402 403 static void i440fx_register_types(void) 404 { 405 type_register_static(&i440fx_info); 406 type_register_static(&i440fx_pcihost_info); 407 } 408 409 type_init(i440fx_register_types) 410