1 /* 2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac) 3 * 4 * Copyright (c) 2006-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/pci/pci_host.h" 28 #include "hw/ppc/mac.h" 29 #include "hw/pci/pci.h" 30 #include "trace.h" 31 32 #define GRACKLE_PCI_HOST_BRIDGE(obj) \ 33 OBJECT_CHECK(GrackleState, (obj), TYPE_GRACKLE_PCI_HOST_BRIDGE) 34 35 typedef struct GrackleState { 36 PCIHostState parent_obj; 37 38 MemoryRegion pci_mmio; 39 MemoryRegion pci_hole; 40 } GrackleState; 41 42 /* Don't know if this matches real hardware, but it agrees with OHW. */ 43 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) 44 { 45 return (irq_num + (pci_dev->devfn >> 3)) & 3; 46 } 47 48 static void pci_grackle_set_irq(void *opaque, int irq_num, int level) 49 { 50 qemu_irq *pic = opaque; 51 52 trace_grackle_set_irq(irq_num, level); 53 qemu_set_irq(pic[irq_num + 0x15], level); 54 } 55 56 PCIBus *pci_grackle_init(uint32_t base, qemu_irq *pic, 57 MemoryRegion *address_space_mem, 58 MemoryRegion *address_space_io) 59 { 60 DeviceState *dev; 61 SysBusDevice *s; 62 PCIHostState *phb; 63 GrackleState *d; 64 65 dev = qdev_create(NULL, TYPE_GRACKLE_PCI_HOST_BRIDGE); 66 s = SYS_BUS_DEVICE(dev); 67 phb = PCI_HOST_BRIDGE(dev); 68 d = GRACKLE_PCI_HOST_BRIDGE(dev); 69 70 memory_region_init(&d->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); 71 memory_region_init_alias(&d->pci_hole, OBJECT(s), "pci-hole", &d->pci_mmio, 72 0x80000000ULL, 0x7e000000ULL); 73 memory_region_add_subregion(address_space_mem, 0x80000000ULL, 74 &d->pci_hole); 75 76 phb->bus = pci_register_root_bus(dev, NULL, 77 pci_grackle_set_irq, 78 pci_grackle_map_irq, 79 pic, 80 &d->pci_mmio, 81 address_space_io, 82 0, 4, TYPE_PCI_BUS); 83 84 pci_create_simple(phb->bus, 0, "grackle"); 85 qdev_init_nofail(dev); 86 87 sysbus_mmio_map(s, 0, base); 88 sysbus_mmio_map(s, 1, base + 0x00200000); 89 90 return phb->bus; 91 } 92 93 static int pci_grackle_init_device(SysBusDevice *dev) 94 { 95 PCIHostState *phb; 96 97 phb = PCI_HOST_BRIDGE(dev); 98 99 memory_region_init_io(&phb->conf_mem, OBJECT(dev), &pci_host_conf_le_ops, 100 dev, "pci-conf-idx", 0x1000); 101 memory_region_init_io(&phb->data_mem, OBJECT(dev), &pci_host_data_le_ops, 102 dev, "pci-data-idx", 0x1000); 103 sysbus_init_mmio(dev, &phb->conf_mem); 104 sysbus_init_mmio(dev, &phb->data_mem); 105 106 return 0; 107 } 108 109 static void grackle_pci_host_realize(PCIDevice *d, Error **errp) 110 { 111 d->config[0x09] = 0x01; 112 } 113 114 static void grackle_pci_class_init(ObjectClass *klass, void *data) 115 { 116 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 117 DeviceClass *dc = DEVICE_CLASS(klass); 118 119 k->realize = grackle_pci_host_realize; 120 k->vendor_id = PCI_VENDOR_ID_MOTOROLA; 121 k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106; 122 k->revision = 0x00; 123 k->class_id = PCI_CLASS_BRIDGE_HOST; 124 /* 125 * PCI-facing part of the host bridge, not usable without the 126 * host-facing part, which can't be device_add'ed, yet. 127 */ 128 dc->user_creatable = false; 129 } 130 131 static const TypeInfo grackle_pci_info = { 132 .name = "grackle", 133 .parent = TYPE_PCI_DEVICE, 134 .instance_size = sizeof(PCIDevice), 135 .class_init = grackle_pci_class_init, 136 .interfaces = (InterfaceInfo[]) { 137 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 138 { }, 139 }, 140 }; 141 142 static void pci_grackle_class_init(ObjectClass *klass, void *data) 143 { 144 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 145 DeviceClass *dc = DEVICE_CLASS(klass); 146 147 k->init = pci_grackle_init_device; 148 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 149 } 150 151 static const TypeInfo grackle_pci_host_info = { 152 .name = TYPE_GRACKLE_PCI_HOST_BRIDGE, 153 .parent = TYPE_PCI_HOST_BRIDGE, 154 .instance_size = sizeof(GrackleState), 155 .class_init = pci_grackle_class_init, 156 }; 157 158 static void grackle_register_types(void) 159 { 160 type_register_static(&grackle_pci_info); 161 type_register_static(&grackle_pci_host_info); 162 } 163 164 type_init(grackle_register_types) 165