1 /* 2 * QEMU Grackle PCI host (heathrow OldWorld PowerMac) 3 * 4 * Copyright (c) 2006-2007 Fabrice Bellard 5 * Copyright (c) 2007 Jocelyn Mayer 6 * 7 * Permission is hereby granted, free of charge, to any person obtaining a copy 8 * of this software and associated documentation files (the "Software"), to deal 9 * in the Software without restriction, including without limitation the rights 10 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 11 * copies of the Software, and to permit persons to whom the Software is 12 * furnished to do so, subject to the following conditions: 13 * 14 * The above copyright notice and this permission notice shall be included in 15 * all copies or substantial portions of the Software. 16 * 17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 22 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 23 * THE SOFTWARE. 24 */ 25 26 #include "qemu/osdep.h" 27 #include "hw/pci/pci_host.h" 28 #include "hw/ppc/mac.h" 29 #include "hw/pci/pci.h" 30 #include "hw/intc/heathrow_pic.h" 31 #include "qapi/error.h" 32 #include "qemu/module.h" 33 #include "trace.h" 34 35 #define GRACKLE_PCI_HOST_BRIDGE(obj) \ 36 OBJECT_CHECK(GrackleState, (obj), TYPE_GRACKLE_PCI_HOST_BRIDGE) 37 38 typedef struct GrackleState { 39 PCIHostState parent_obj; 40 41 uint32_t ofw_addr; 42 HeathrowState *pic; 43 qemu_irq irqs[4]; 44 MemoryRegion pci_mmio; 45 MemoryRegion pci_hole; 46 MemoryRegion pci_io; 47 } GrackleState; 48 49 /* Don't know if this matches real hardware, but it agrees with OHW. */ 50 static int pci_grackle_map_irq(PCIDevice *pci_dev, int irq_num) 51 { 52 return (irq_num + (pci_dev->devfn >> 3)) & 3; 53 } 54 55 static void pci_grackle_set_irq(void *opaque, int irq_num, int level) 56 { 57 GrackleState *s = opaque; 58 59 trace_grackle_set_irq(irq_num, level); 60 qemu_set_irq(s->irqs[irq_num], level); 61 } 62 63 static void grackle_init_irqs(GrackleState *s) 64 { 65 int i; 66 67 for (i = 0; i < ARRAY_SIZE(s->irqs); i++) { 68 s->irqs[i] = qdev_get_gpio_in(DEVICE(s->pic), 0x15 + i); 69 } 70 } 71 72 static void grackle_realize(DeviceState *dev, Error **errp) 73 { 74 GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev); 75 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 76 77 phb->bus = pci_register_root_bus(dev, NULL, 78 pci_grackle_set_irq, 79 pci_grackle_map_irq, 80 s, 81 &s->pci_mmio, 82 &s->pci_io, 83 0, 4, TYPE_PCI_BUS); 84 85 pci_create_simple(phb->bus, 0, "grackle"); 86 grackle_init_irqs(s); 87 } 88 89 static void grackle_init(Object *obj) 90 { 91 GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(obj); 92 SysBusDevice *sbd = SYS_BUS_DEVICE(obj); 93 PCIHostState *phb = PCI_HOST_BRIDGE(obj); 94 95 memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); 96 memory_region_init_io(&s->pci_io, OBJECT(s), &unassigned_io_ops, obj, 97 "pci-isa-mmio", 0x00200000); 98 99 memory_region_init_alias(&s->pci_hole, OBJECT(s), "pci-hole", &s->pci_mmio, 100 0x80000000ULL, 0x7e000000ULL); 101 102 memory_region_init_io(&phb->conf_mem, obj, &pci_host_conf_le_ops, 103 DEVICE(obj), "pci-conf-idx", 0x1000); 104 memory_region_init_io(&phb->data_mem, obj, &pci_host_data_le_ops, 105 DEVICE(obj), "pci-data-idx", 0x1000); 106 107 object_property_add_link(obj, "pic", TYPE_HEATHROW, 108 (Object **) &s->pic, 109 qdev_prop_allow_set_link_before_realize, 110 0, NULL); 111 112 sysbus_init_mmio(sbd, &phb->conf_mem); 113 sysbus_init_mmio(sbd, &phb->data_mem); 114 sysbus_init_mmio(sbd, &s->pci_hole); 115 sysbus_init_mmio(sbd, &s->pci_io); 116 } 117 118 static void grackle_pci_realize(PCIDevice *d, Error **errp) 119 { 120 d->config[0x09] = 0x01; 121 } 122 123 static void grackle_pci_class_init(ObjectClass *klass, void *data) 124 { 125 DeviceClass *dc = DEVICE_CLASS(klass); 126 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 127 128 k->realize = grackle_pci_realize; 129 k->vendor_id = PCI_VENDOR_ID_MOTOROLA; 130 k->device_id = PCI_DEVICE_ID_MOTOROLA_MPC106; 131 k->revision = 0x00; 132 k->class_id = PCI_CLASS_BRIDGE_HOST; 133 /* 134 * PCI-facing part of the host bridge, not usable without the 135 * host-facing part, which can't be device_add'ed, yet. 136 */ 137 dc->user_creatable = false; 138 } 139 140 static const TypeInfo grackle_pci_info = { 141 .name = "grackle", 142 .parent = TYPE_PCI_DEVICE, 143 .instance_size = sizeof(PCIDevice), 144 .class_init = grackle_pci_class_init, 145 .interfaces = (InterfaceInfo[]) { 146 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 147 { }, 148 }, 149 }; 150 151 static char *grackle_ofw_unit_address(const SysBusDevice *dev) 152 { 153 GrackleState *s = GRACKLE_PCI_HOST_BRIDGE(dev); 154 155 return g_strdup_printf("%x", s->ofw_addr); 156 } 157 158 static Property grackle_properties[] = { 159 DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1), 160 DEFINE_PROP_END_OF_LIST() 161 }; 162 163 static void grackle_class_init(ObjectClass *klass, void *data) 164 { 165 DeviceClass *dc = DEVICE_CLASS(klass); 166 SysBusDeviceClass *sbc = SYS_BUS_DEVICE_CLASS(klass); 167 168 dc->realize = grackle_realize; 169 dc->props = grackle_properties; 170 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 171 dc->fw_name = "pci"; 172 sbc->explicit_ofw_unit_address = grackle_ofw_unit_address; 173 } 174 175 static const TypeInfo grackle_host_info = { 176 .name = TYPE_GRACKLE_PCI_HOST_BRIDGE, 177 .parent = TYPE_PCI_HOST_BRIDGE, 178 .instance_size = sizeof(GrackleState), 179 .instance_init = grackle_init, 180 .class_init = grackle_class_init, 181 }; 182 183 static void grackle_register_types(void) 184 { 185 type_register_static(&grackle_pci_info); 186 type_register_static(&grackle_host_info); 187 } 188 189 type_init(grackle_register_types) 190