1 /* 2 * QEMU Generic PCI Express Bridge Emulation 3 * 4 * Copyright (C) 2015 Alexander Graf <agraf@suse.de> 5 * 6 * Code loosely based on q35.c. 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 * 26 * Check out these documents for more information on the device: 27 * 28 * http://www.kernel.org/doc/Documentation/devicetree/bindings/pci/host-generic-pci.txt 29 * http://www.firmware.org/1275/practice/imap/imap0_9d.pdf 30 */ 31 32 #include "qemu/osdep.h" 33 #include "qapi/error.h" 34 #include "hw/hw.h" 35 #include "hw/pci-host/gpex.h" 36 #include "qemu/module.h" 37 38 /**************************************************************************** 39 * GPEX host 40 */ 41 42 static void gpex_set_irq(void *opaque, int irq_num, int level) 43 { 44 GPEXHost *s = opaque; 45 46 qemu_set_irq(s->irq[irq_num], level); 47 } 48 49 int gpex_set_irq_num(GPEXHost *s, int index, int gsi) 50 { 51 if (index >= GPEX_NUM_IRQS) { 52 return -EINVAL; 53 } 54 55 s->irq_num[index] = gsi; 56 return 0; 57 } 58 59 static PCIINTxRoute gpex_route_intx_pin_to_irq(void *opaque, int pin) 60 { 61 PCIINTxRoute route; 62 GPEXHost *s = opaque; 63 int gsi = s->irq_num[pin]; 64 65 route.irq = gsi; 66 if (gsi < 0) { 67 route.mode = PCI_INTX_DISABLED; 68 } else { 69 route.mode = PCI_INTX_ENABLED; 70 } 71 72 return route; 73 } 74 75 static void gpex_host_realize(DeviceState *dev, Error **errp) 76 { 77 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 78 GPEXHost *s = GPEX_HOST(dev); 79 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 80 PCIExpressHost *pex = PCIE_HOST_BRIDGE(dev); 81 int i; 82 83 pcie_host_mmcfg_init(pex, PCIE_MMCFG_SIZE_MAX); 84 memory_region_init(&s->io_mmio, OBJECT(s), "gpex_mmio", UINT64_MAX); 85 memory_region_init(&s->io_ioport, OBJECT(s), "gpex_ioport", 64 * 1024); 86 87 sysbus_init_mmio(sbd, &pex->mmio); 88 sysbus_init_mmio(sbd, &s->io_mmio); 89 sysbus_init_mmio(sbd, &s->io_ioport); 90 for (i = 0; i < GPEX_NUM_IRQS; i++) { 91 sysbus_init_irq(sbd, &s->irq[i]); 92 s->irq_num[i] = -1; 93 } 94 95 pci->bus = pci_register_root_bus(dev, "pcie.0", gpex_set_irq, 96 pci_swizzle_map_irq_fn, s, &s->io_mmio, 97 &s->io_ioport, 0, 4, TYPE_PCIE_BUS); 98 99 qdev_set_parent_bus(DEVICE(&s->gpex_root), BUS(pci->bus)); 100 pci_bus_set_route_irq_fn(pci->bus, gpex_route_intx_pin_to_irq); 101 qdev_init_nofail(DEVICE(&s->gpex_root)); 102 } 103 104 static const char *gpex_host_root_bus_path(PCIHostState *host_bridge, 105 PCIBus *rootbus) 106 { 107 return "0000:00"; 108 } 109 110 static void gpex_host_class_init(ObjectClass *klass, void *data) 111 { 112 DeviceClass *dc = DEVICE_CLASS(klass); 113 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 114 115 hc->root_bus_path = gpex_host_root_bus_path; 116 dc->realize = gpex_host_realize; 117 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 118 dc->fw_name = "pci"; 119 } 120 121 static void gpex_host_initfn(Object *obj) 122 { 123 GPEXHost *s = GPEX_HOST(obj); 124 GPEXRootState *root = &s->gpex_root; 125 126 object_initialize_child(obj, "gpex_root", root, sizeof(*root), 127 TYPE_GPEX_ROOT_DEVICE, &error_abort, NULL); 128 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); 129 qdev_prop_set_bit(DEVICE(root), "multifunction", false); 130 } 131 132 static const TypeInfo gpex_host_info = { 133 .name = TYPE_GPEX_HOST, 134 .parent = TYPE_PCIE_HOST_BRIDGE, 135 .instance_size = sizeof(GPEXHost), 136 .instance_init = gpex_host_initfn, 137 .class_init = gpex_host_class_init, 138 }; 139 140 /**************************************************************************** 141 * GPEX Root D0:F0 142 */ 143 144 static const VMStateDescription vmstate_gpex_root = { 145 .name = "gpex_root", 146 .version_id = 1, 147 .minimum_version_id = 1, 148 .fields = (VMStateField[]) { 149 VMSTATE_PCI_DEVICE(parent_obj, GPEXRootState), 150 VMSTATE_END_OF_LIST() 151 } 152 }; 153 154 static void gpex_root_class_init(ObjectClass *klass, void *data) 155 { 156 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 157 DeviceClass *dc = DEVICE_CLASS(klass); 158 159 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 160 dc->desc = "QEMU generic PCIe host bridge"; 161 dc->vmsd = &vmstate_gpex_root; 162 k->vendor_id = PCI_VENDOR_ID_REDHAT; 163 k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_HOST; 164 k->revision = 0; 165 k->class_id = PCI_CLASS_BRIDGE_HOST; 166 /* 167 * PCI-facing part of the host bridge, not usable without the 168 * host-facing part, which can't be device_add'ed, yet. 169 */ 170 dc->user_creatable = false; 171 } 172 173 static const TypeInfo gpex_root_info = { 174 .name = TYPE_GPEX_ROOT_DEVICE, 175 .parent = TYPE_PCI_DEVICE, 176 .instance_size = sizeof(GPEXRootState), 177 .class_init = gpex_root_class_init, 178 .interfaces = (InterfaceInfo[]) { 179 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 180 { }, 181 }, 182 }; 183 184 static void gpex_register(void) 185 { 186 type_register_static(&gpex_root_info); 187 type_register_static(&gpex_host_info); 188 } 189 190 type_init(gpex_register) 191