1 #include "qemu/osdep.h" 2 #include "hw/acpi/aml-build.h" 3 #include "hw/pci-host/gpex.h" 4 #include "hw/arm/virt.h" 5 #include "hw/pci/pci_bus.h" 6 #include "hw/pci/pci_bridge.h" 7 #include "hw/pci/pcie_host.h" 8 #include "hw/acpi/cxl.h" 9 10 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq, 11 Aml *scope, uint8_t bus_num) 12 { 13 Aml *method, *crs; 14 int i, slot_no; 15 16 /* Declare the PCI Routing Table. */ 17 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); 18 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { 19 for (i = 0; i < PCI_NUM_PINS; i++) { 20 int gsi = (i + slot_no) % PCI_NUM_PINS; 21 Aml *pkg = aml_package(4); 22 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); 23 aml_append(pkg, aml_int(i)); 24 aml_append(pkg, aml_name("L%.02X%X", bus_num, gsi)); 25 aml_append(pkg, aml_int(0)); 26 aml_append(rt_pkg, pkg); 27 } 28 } 29 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 30 31 /* Create GSI link device */ 32 for (i = 0; i < PCI_NUM_PINS; i++) { 33 uint32_t irqs = irq + i; 34 Aml *dev_gsi = aml_device("L%.02X%X", bus_num, i); 35 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 36 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); 37 crs = aml_resource_template(); 38 aml_append(crs, 39 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 40 AML_EXCLUSIVE, &irqs, 1)); 41 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 42 crs = aml_resource_template(); 43 aml_append(crs, 44 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 45 AML_EXCLUSIVE, &irqs, 1)); 46 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 47 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 48 aml_append(dev_gsi, method); 49 aml_append(scope, dev_gsi); 50 } 51 } 52 53 static Aml *build_host_bridge_osc(bool enable_native_pcie_hotplug) 54 { 55 Aml *method, *UUID, *ifctx, *ifctx1, *elsectx; 56 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 57 aml_append(method, aml_name_decl("SUPP", aml_int(0))); 58 aml_append(method, aml_name_decl("CTRL", aml_int(0))); 59 aml_append(method, 60 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 61 62 /* PCI Firmware Specification 3.0 63 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 64 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 65 * identified by the Universal Unique IDentifier (UUID) 66 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 67 */ 68 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 69 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 70 aml_append(ifctx, 71 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 72 aml_append(ifctx, 73 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 74 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 75 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 76 77 /* 78 * Allow OS control for SHPCHotplug, PME, AER, PCIeCapability, 79 * and PCIeHotplug depending on enable_native_pcie_hotplug 80 */ 81 aml_append(ifctx, aml_and(aml_name("CTRL"), 82 aml_int(0x1E | (enable_native_pcie_hotplug ? 0x1 : 0x0)), 83 aml_name("CTRL"))); 84 85 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 86 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), 87 aml_name("CDW1"))); 88 aml_append(ifctx, ifctx1); 89 90 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 91 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), 92 aml_name("CDW1"))); 93 aml_append(ifctx, ifctx1); 94 95 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 96 aml_append(ifctx, aml_return(aml_arg(3))); 97 aml_append(method, ifctx); 98 99 elsectx = aml_else(); 100 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), 101 aml_name("CDW1"))); 102 aml_append(elsectx, aml_return(aml_arg(3))); 103 aml_append(method, elsectx); 104 return method; 105 } 106 107 static Aml *build_host_bridge_dsm(void) 108 { 109 Aml *method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 110 Aml *UUID, *ifctx, *ifctx1, *buf; 111 112 /* PCI Firmware Specification 3.0 113 * 4.6.1. _DSM for PCI Express Slot Information 114 * The UUID in _DSM in this context is 115 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 116 */ 117 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 118 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 119 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 120 uint8_t byte_list[1] = {1}; 121 buf = aml_buffer(1, byte_list); 122 aml_append(ifctx1, aml_return(buf)); 123 aml_append(ifctx, ifctx1); 124 aml_append(method, ifctx); 125 126 byte_list[0] = 0; 127 buf = aml_buffer(1, byte_list); 128 aml_append(method, aml_return(buf)); 129 return method; 130 } 131 132 static void acpi_dsdt_add_host_bridge_methods(Aml *dev, 133 bool enable_native_pcie_hotplug) 134 { 135 /* Declare an _OSC (OS Control Handoff) method */ 136 aml_append(dev, build_host_bridge_osc(enable_native_pcie_hotplug)); 137 aml_append(dev, build_host_bridge_dsm()); 138 } 139 140 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) 141 { 142 int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; 143 Aml *method, *crs, *dev, *rbuf; 144 PCIBus *bus = cfg->bus; 145 CrsRangeSet crs_range_set; 146 CrsRangeEntry *entry; 147 int i; 148 149 /* start to construct the tables for pxb */ 150 crs_range_set_init(&crs_range_set); 151 if (bus) { 152 QLIST_FOREACH(bus, &bus->child, sibling) { 153 uint8_t bus_num = pci_bus_num(bus); 154 uint8_t numa_node = pci_bus_numa_node(bus); 155 uint32_t uid; 156 bool is_cxl = pci_bus_is_cxl(bus); 157 158 if (!pci_bus_is_root(bus)) { 159 continue; 160 } 161 162 /* 163 * 0 - (nr_pcie_buses - 1) is the bus range for the main 164 * host-bridge and it equals the MIN of the 165 * busNr defined for pxb-pcie. 166 */ 167 if (bus_num < nr_pcie_buses) { 168 nr_pcie_buses = bus_num; 169 } 170 171 uid = object_property_get_uint(OBJECT(bus), "acpi_uid", 172 &error_fatal); 173 dev = aml_device("PC%.02X", bus_num); 174 if (is_cxl) { 175 struct Aml *pkg = aml_package(2); 176 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 177 aml_append(pkg, aml_eisaid("PNP0A08")); 178 aml_append(pkg, aml_eisaid("PNP0A03")); 179 aml_append(dev, aml_name_decl("_CID", pkg)); 180 } else { 181 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 182 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 183 } 184 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 185 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 186 aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"))); 187 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 188 if (numa_node != NUMA_NODE_UNASSIGNED) { 189 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 190 } 191 192 acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num); 193 194 /* 195 * Resources defined for PXBs are composed of the following parts: 196 * 1. The resources the pci-bridge/pcie-root-port need. 197 * 2. The resources the devices behind pxb need. 198 */ 199 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 200 cfg->pio.base, 0, 0, 0); 201 aml_append(dev, aml_name_decl("_CRS", crs)); 202 203 if (is_cxl) { 204 build_cxl_osc_method(dev); 205 } else { 206 /* pxb bridges do not have ACPI PCI Hot-plug enabled */ 207 acpi_dsdt_add_host_bridge_methods(dev, true); 208 } 209 210 aml_append(scope, dev); 211 } 212 } 213 214 /* tables for the main */ 215 dev = aml_device("%s", "PCI0"); 216 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 217 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 218 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 219 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 220 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 221 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 222 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 223 224 acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0); 225 226 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 227 aml_append(method, aml_return(aml_int(cfg->ecam.base))); 228 aml_append(dev, method); 229 230 /* 231 * At this point crs_range_set has all the ranges used by pci 232 * busses *other* than PCI0. These ranges will be excluded from 233 * the PCI0._CRS. 234 */ 235 rbuf = aml_resource_template(); 236 aml_append(rbuf, 237 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 238 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 239 nr_pcie_buses)); 240 if (cfg->mmio32.size) { 241 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 242 cfg->mmio32.base, 243 cfg->mmio32.base + cfg->mmio32.size - 1); 244 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 245 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 246 aml_append(rbuf, 247 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 248 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 249 entry->base, entry->limit, 250 0x0000, entry->limit - entry->base + 1)); 251 } 252 } 253 if (cfg->pio.size) { 254 crs_replace_with_free_ranges(crs_range_set.io_ranges, 255 0x0000, 256 cfg->pio.size - 1); 257 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 258 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 259 aml_append(rbuf, 260 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 261 AML_ENTIRE_RANGE, 0x0000, entry->base, 262 entry->limit, cfg->pio.base, 263 entry->limit - entry->base + 1)); 264 } 265 } 266 if (cfg->mmio64.size) { 267 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 268 cfg->mmio64.base, 269 cfg->mmio64.base + cfg->mmio64.size - 1); 270 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 271 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 272 aml_append(rbuf, 273 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 274 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 275 entry->base, 276 entry->limit, 0x0000, 277 entry->limit - entry->base + 1)); 278 } 279 } 280 aml_append(dev, aml_name_decl("_CRS", rbuf)); 281 282 acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug); 283 284 Aml *dev_res0 = aml_device("%s", "RES0"); 285 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 286 crs = aml_resource_template(); 287 aml_append(crs, 288 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 289 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 290 cfg->ecam.base, 291 cfg->ecam.base + cfg->ecam.size - 1, 292 0x0000, 293 cfg->ecam.size)); 294 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 295 aml_append(dev, dev_res0); 296 aml_append(scope, dev); 297 298 crs_range_set_free(&crs_range_set); 299 } 300 301 void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq) 302 { 303 bool ambig; 304 Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig); 305 306 if (!obj || ambig) { 307 return; 308 } 309 310 GPEX_HOST(obj)->gpex_cfg.irq = irq; 311 acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); 312 } 313