1 #include "qemu/osdep.h" 2 #include "hw/acpi/aml-build.h" 3 #include "hw/pci-host/gpex.h" 4 5 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) 6 { 7 int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; 8 Aml *method, *crs, *ifctx, *UUID, *ifctx1, *elsectx, *buf; 9 int i, slot_no; 10 11 Aml *dev = aml_device("%s", "PCI0"); 12 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 13 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 14 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 15 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 16 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 17 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 18 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 19 20 /* Declare the PCI Routing Table. */ 21 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); 22 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { 23 for (i = 0; i < PCI_NUM_PINS; i++) { 24 int gsi = (i + slot_no) % PCI_NUM_PINS; 25 Aml *pkg = aml_package(4); 26 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); 27 aml_append(pkg, aml_int(i)); 28 aml_append(pkg, aml_name("GSI%d", gsi)); 29 aml_append(pkg, aml_int(0)); 30 aml_append(rt_pkg, pkg); 31 } 32 } 33 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 34 35 /* Create GSI link device */ 36 for (i = 0; i < PCI_NUM_PINS; i++) { 37 uint32_t irqs = cfg->irq + i; 38 Aml *dev_gsi = aml_device("GSI%d", i); 39 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 40 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); 41 crs = aml_resource_template(); 42 aml_append(crs, 43 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 44 AML_EXCLUSIVE, &irqs, 1)); 45 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 46 crs = aml_resource_template(); 47 aml_append(crs, 48 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 49 AML_EXCLUSIVE, &irqs, 1)); 50 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 51 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 52 aml_append(dev_gsi, method); 53 aml_append(dev, dev_gsi); 54 } 55 56 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 57 aml_append(method, aml_return(aml_int(cfg->ecam.base))); 58 aml_append(dev, method); 59 60 method = aml_method("_CRS", 0, AML_NOTSERIALIZED); 61 Aml *rbuf = aml_resource_template(); 62 aml_append(rbuf, 63 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 64 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 65 nr_pcie_buses)); 66 if (cfg->mmio32.size) { 67 aml_append(rbuf, 68 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 69 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 70 cfg->mmio32.base, 71 cfg->mmio32.base + cfg->mmio32.size - 1, 72 0x0000, 73 cfg->mmio32.size)); 74 } 75 if (cfg->pio.size) { 76 aml_append(rbuf, 77 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 78 AML_ENTIRE_RANGE, 0x0000, 0x0000, 79 cfg->pio.size - 1, 80 cfg->pio.base, 81 cfg->pio.size)); 82 } 83 if (cfg->mmio64.size) { 84 aml_append(rbuf, 85 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 86 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 87 cfg->mmio64.base, 88 cfg->mmio64.base + cfg->mmio64.size - 1, 89 0x0000, 90 cfg->mmio64.size)); 91 } 92 aml_append(method, aml_return(rbuf)); 93 aml_append(dev, method); 94 95 /* Declare an _OSC (OS Control Handoff) method */ 96 aml_append(dev, aml_name_decl("SUPP", aml_int(0))); 97 aml_append(dev, aml_name_decl("CTRL", aml_int(0))); 98 method = aml_method("_OSC", 4, AML_NOTSERIALIZED); 99 aml_append(method, 100 aml_create_dword_field(aml_arg(3), aml_int(0), "CDW1")); 101 102 /* PCI Firmware Specification 3.0 103 * 4.5.1. _OSC Interface for PCI Host Bridge Devices 104 * The _OSC interface for a PCI/PCI-X/PCI Express hierarchy is 105 * identified by the Universal Unique IDentifier (UUID) 106 * 33DB4D5B-1FF7-401C-9657-7441C03DD766 107 */ 108 UUID = aml_touuid("33DB4D5B-1FF7-401C-9657-7441C03DD766"); 109 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 110 aml_append(ifctx, 111 aml_create_dword_field(aml_arg(3), aml_int(4), "CDW2")); 112 aml_append(ifctx, 113 aml_create_dword_field(aml_arg(3), aml_int(8), "CDW3")); 114 aml_append(ifctx, aml_store(aml_name("CDW2"), aml_name("SUPP"))); 115 aml_append(ifctx, aml_store(aml_name("CDW3"), aml_name("CTRL"))); 116 117 /* 118 * Allow OS control for all 5 features: 119 * PCIeHotplug SHPCHotplug PME AER PCIeCapability. 120 */ 121 aml_append(ifctx, aml_and(aml_name("CTRL"), aml_int(0x1F), 122 aml_name("CTRL"))); 123 124 ifctx1 = aml_if(aml_lnot(aml_equal(aml_arg(1), aml_int(0x1)))); 125 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x08), 126 aml_name("CDW1"))); 127 aml_append(ifctx, ifctx1); 128 129 ifctx1 = aml_if(aml_lnot(aml_equal(aml_name("CDW3"), aml_name("CTRL")))); 130 aml_append(ifctx1, aml_or(aml_name("CDW1"), aml_int(0x10), 131 aml_name("CDW1"))); 132 aml_append(ifctx, ifctx1); 133 134 aml_append(ifctx, aml_store(aml_name("CTRL"), aml_name("CDW3"))); 135 aml_append(ifctx, aml_return(aml_arg(3))); 136 aml_append(method, ifctx); 137 138 elsectx = aml_else(); 139 aml_append(elsectx, aml_or(aml_name("CDW1"), aml_int(4), 140 aml_name("CDW1"))); 141 aml_append(elsectx, aml_return(aml_arg(3))); 142 aml_append(method, elsectx); 143 aml_append(dev, method); 144 145 method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 146 147 /* PCI Firmware Specification 3.0 148 * 4.6.1. _DSM for PCI Express Slot Information 149 * The UUID in _DSM in this context is 150 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 151 */ 152 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 153 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 154 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 155 uint8_t byte_list[1] = {1}; 156 buf = aml_buffer(1, byte_list); 157 aml_append(ifctx1, aml_return(buf)); 158 aml_append(ifctx, ifctx1); 159 aml_append(method, ifctx); 160 161 byte_list[0] = 0; 162 buf = aml_buffer(1, byte_list); 163 aml_append(method, aml_return(buf)); 164 aml_append(dev, method); 165 166 Aml *dev_res0 = aml_device("%s", "RES0"); 167 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 168 crs = aml_resource_template(); 169 aml_append(crs, 170 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 171 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 172 cfg->ecam.base, 173 cfg->ecam.base + cfg->ecam.size - 1, 174 0x0000, 175 cfg->ecam.size)); 176 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 177 aml_append(dev, dev_res0); 178 aml_append(scope, dev); 179 } 180