1 #include "qemu/osdep.h" 2 #include "hw/acpi/aml-build.h" 3 #include "hw/acpi/pci.h" 4 #include "hw/pci-host/gpex.h" 5 #include "hw/arm/virt.h" 6 #include "hw/pci/pci_bus.h" 7 #include "hw/pci/pci_bridge.h" 8 #include "hw/pci/pcie_host.h" 9 #include "hw/acpi/cxl.h" 10 11 static void acpi_dsdt_add_pci_route_table(Aml *dev, uint32_t irq, 12 Aml *scope, uint8_t bus_num) 13 { 14 Aml *method, *crs; 15 int i, slot_no; 16 17 /* Declare the PCI Routing Table. */ 18 Aml *rt_pkg = aml_varpackage(PCI_SLOT_MAX * PCI_NUM_PINS); 19 for (slot_no = 0; slot_no < PCI_SLOT_MAX; slot_no++) { 20 for (i = 0; i < PCI_NUM_PINS; i++) { 21 int gsi = (i + slot_no) % PCI_NUM_PINS; 22 Aml *pkg = aml_package(4); 23 aml_append(pkg, aml_int((slot_no << 16) | 0xFFFF)); 24 aml_append(pkg, aml_int(i)); 25 aml_append(pkg, aml_name("L%.02X%X", bus_num, gsi)); 26 aml_append(pkg, aml_int(0)); 27 aml_append(rt_pkg, pkg); 28 } 29 } 30 aml_append(dev, aml_name_decl("_PRT", rt_pkg)); 31 32 /* Create GSI link device */ 33 for (i = 0; i < PCI_NUM_PINS; i++) { 34 uint32_t irqs = irq + i; 35 Aml *dev_gsi = aml_device("L%.02X%X", bus_num, i); 36 aml_append(dev_gsi, aml_name_decl("_HID", aml_string("PNP0C0F"))); 37 aml_append(dev_gsi, aml_name_decl("_UID", aml_int(i))); 38 crs = aml_resource_template(); 39 aml_append(crs, 40 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 41 AML_EXCLUSIVE, &irqs, 1)); 42 aml_append(dev_gsi, aml_name_decl("_PRS", crs)); 43 crs = aml_resource_template(); 44 aml_append(crs, 45 aml_interrupt(AML_CONSUMER, AML_LEVEL, AML_ACTIVE_HIGH, 46 AML_EXCLUSIVE, &irqs, 1)); 47 aml_append(dev_gsi, aml_name_decl("_CRS", crs)); 48 method = aml_method("_SRS", 1, AML_NOTSERIALIZED); 49 aml_append(dev_gsi, method); 50 aml_append(scope, dev_gsi); 51 } 52 } 53 54 static Aml *build_pci_host_bridge_dsm_method(void) 55 { 56 Aml *method = aml_method("_DSM", 4, AML_NOTSERIALIZED); 57 Aml *UUID, *ifctx, *ifctx1, *buf; 58 59 /* PCI Firmware Specification 3.0 60 * 4.6.1. _DSM for PCI Express Slot Information 61 * The UUID in _DSM in this context is 62 * {E5C937D0-3553-4D7A-9117-EA4D19C3434D} 63 */ 64 UUID = aml_touuid("E5C937D0-3553-4D7A-9117-EA4D19C3434D"); 65 ifctx = aml_if(aml_equal(aml_arg(0), UUID)); 66 ifctx1 = aml_if(aml_equal(aml_arg(2), aml_int(0))); 67 uint8_t byte_list[1] = {1}; 68 buf = aml_buffer(1, byte_list); 69 aml_append(ifctx1, aml_return(buf)); 70 aml_append(ifctx, ifctx1); 71 aml_append(method, ifctx); 72 73 byte_list[0] = 0; 74 buf = aml_buffer(1, byte_list); 75 aml_append(method, aml_return(buf)); 76 return method; 77 } 78 79 static void acpi_dsdt_add_host_bridge_methods(Aml *dev, 80 bool enable_native_pcie_hotplug) 81 { 82 /* Declare an _OSC (OS Control Handoff) method */ 83 aml_append(dev, 84 build_pci_host_bridge_osc_method(enable_native_pcie_hotplug)); 85 aml_append(dev, build_pci_host_bridge_dsm_method()); 86 } 87 88 void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) 89 { 90 int nr_pcie_buses = cfg->ecam.size / PCIE_MMCFG_SIZE_MIN; 91 Aml *method, *crs, *dev, *rbuf; 92 PCIBus *bus = cfg->bus; 93 CrsRangeSet crs_range_set; 94 CrsRangeEntry *entry; 95 int i; 96 97 /* start to construct the tables for pxb */ 98 crs_range_set_init(&crs_range_set); 99 if (bus) { 100 QLIST_FOREACH(bus, &bus->child, sibling) { 101 uint8_t bus_num = pci_bus_num(bus); 102 uint8_t numa_node = pci_bus_numa_node(bus); 103 uint32_t uid; 104 bool is_cxl = pci_bus_is_cxl(bus); 105 106 if (!pci_bus_is_root(bus)) { 107 continue; 108 } 109 110 /* 111 * 0 - (nr_pcie_buses - 1) is the bus range for the main 112 * host-bridge and it equals the MIN of the 113 * busNr defined for pxb-pcie. 114 */ 115 if (bus_num < nr_pcie_buses) { 116 nr_pcie_buses = bus_num; 117 } 118 119 uid = object_property_get_uint(OBJECT(bus), "acpi_uid", 120 &error_fatal); 121 dev = aml_device("PC%.02X", bus_num); 122 if (is_cxl) { 123 struct Aml *pkg = aml_package(2); 124 aml_append(dev, aml_name_decl("_HID", aml_string("ACPI0016"))); 125 aml_append(pkg, aml_eisaid("PNP0A08")); 126 aml_append(pkg, aml_eisaid("PNP0A03")); 127 aml_append(dev, aml_name_decl("_CID", pkg)); 128 } else { 129 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 130 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 131 } 132 aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); 133 aml_append(dev, aml_name_decl("_UID", aml_int(uid))); 134 aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"))); 135 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 136 if (numa_node != NUMA_NODE_UNASSIGNED) { 137 aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); 138 } 139 140 acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, bus_num); 141 142 /* 143 * Resources defined for PXBs are composed of the following parts: 144 * 1. The resources the pci-bridge/pcie-root-port need. 145 * 2. The resources the devices behind pxb need. 146 */ 147 crs = build_crs(PCI_HOST_BRIDGE(BUS(bus)->parent), &crs_range_set, 148 cfg->pio.base, 0, 0, 0); 149 aml_append(dev, aml_name_decl("_CRS", crs)); 150 151 if (is_cxl) { 152 build_cxl_osc_method(dev); 153 } else { 154 /* pxb bridges do not have ACPI PCI Hot-plug enabled */ 155 acpi_dsdt_add_host_bridge_methods(dev, true); 156 } 157 158 aml_append(scope, dev); 159 } 160 } 161 162 /* tables for the main */ 163 dev = aml_device("%s", "PCI0"); 164 aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A08"))); 165 aml_append(dev, aml_name_decl("_CID", aml_string("PNP0A03"))); 166 aml_append(dev, aml_name_decl("_SEG", aml_int(0))); 167 aml_append(dev, aml_name_decl("_BBN", aml_int(0))); 168 aml_append(dev, aml_name_decl("_UID", aml_int(0))); 169 aml_append(dev, aml_name_decl("_STR", aml_unicode("PCIe 0 Device"))); 170 aml_append(dev, aml_name_decl("_CCA", aml_int(1))); 171 172 acpi_dsdt_add_pci_route_table(dev, cfg->irq, scope, 0); 173 174 method = aml_method("_CBA", 0, AML_NOTSERIALIZED); 175 aml_append(method, aml_return(aml_int(cfg->ecam.base))); 176 aml_append(dev, method); 177 178 /* 179 * At this point crs_range_set has all the ranges used by pci 180 * busses *other* than PCI0. These ranges will be excluded from 181 * the PCI0._CRS. 182 */ 183 rbuf = aml_resource_template(); 184 aml_append(rbuf, 185 aml_word_bus_number(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 186 0x0000, 0x0000, nr_pcie_buses - 1, 0x0000, 187 nr_pcie_buses)); 188 if (cfg->mmio32.size) { 189 crs_replace_with_free_ranges(crs_range_set.mem_ranges, 190 cfg->mmio32.base, 191 cfg->mmio32.base + cfg->mmio32.size - 1); 192 for (i = 0; i < crs_range_set.mem_ranges->len; i++) { 193 entry = g_ptr_array_index(crs_range_set.mem_ranges, i); 194 aml_append(rbuf, 195 aml_dword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 196 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 197 entry->base, entry->limit, 198 0x0000, entry->limit - entry->base + 1)); 199 } 200 } 201 if (cfg->pio.size) { 202 crs_replace_with_free_ranges(crs_range_set.io_ranges, 203 0x0000, 204 cfg->pio.size - 1); 205 for (i = 0; i < crs_range_set.io_ranges->len; i++) { 206 entry = g_ptr_array_index(crs_range_set.io_ranges, i); 207 aml_append(rbuf, 208 aml_dword_io(AML_MIN_FIXED, AML_MAX_FIXED, AML_POS_DECODE, 209 AML_ENTIRE_RANGE, 0x0000, entry->base, 210 entry->limit, cfg->pio.base, 211 entry->limit - entry->base + 1)); 212 } 213 } 214 if (cfg->mmio64.size) { 215 crs_replace_with_free_ranges(crs_range_set.mem_64bit_ranges, 216 cfg->mmio64.base, 217 cfg->mmio64.base + cfg->mmio64.size - 1); 218 for (i = 0; i < crs_range_set.mem_64bit_ranges->len; i++) { 219 entry = g_ptr_array_index(crs_range_set.mem_64bit_ranges, i); 220 aml_append(rbuf, 221 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 222 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 223 entry->base, 224 entry->limit, 0x0000, 225 entry->limit - entry->base + 1)); 226 } 227 } 228 aml_append(dev, aml_name_decl("_CRS", rbuf)); 229 230 acpi_dsdt_add_host_bridge_methods(dev, cfg->pci_native_hotplug); 231 232 Aml *dev_res0 = aml_device("%s", "RES0"); 233 aml_append(dev_res0, aml_name_decl("_HID", aml_string("PNP0C02"))); 234 crs = aml_resource_template(); 235 aml_append(crs, 236 aml_qword_memory(AML_POS_DECODE, AML_MIN_FIXED, AML_MAX_FIXED, 237 AML_NON_CACHEABLE, AML_READ_WRITE, 0x0000, 238 cfg->ecam.base, 239 cfg->ecam.base + cfg->ecam.size - 1, 240 0x0000, 241 cfg->ecam.size)); 242 aml_append(dev_res0, aml_name_decl("_CRS", crs)); 243 aml_append(dev, dev_res0); 244 aml_append(scope, dev); 245 246 crs_range_set_free(&crs_range_set); 247 } 248 249 void acpi_dsdt_add_gpex_host(Aml *scope, uint32_t irq) 250 { 251 bool ambig; 252 Object *obj = object_resolve_path_type("", TYPE_GPEX_HOST, &ambig); 253 254 if (!obj || ambig) { 255 return; 256 } 257 258 GPEX_HOST(obj)->gpex_cfg.irq = irq; 259 acpi_dsdt_add_gpex(scope, &GPEX_HOST(obj)->gpex_cfg); 260 } 261