1 /* 2 * Copyright (c) 2018, Impinj, Inc. 3 * 4 * Designware PCIe IP block emulation 5 * 6 * This library is free software; you can redistribute it and/or 7 * modify it under the terms of the GNU Lesser General Public 8 * License as published by the Free Software Foundation; either 9 * version 2 of the License, or (at your option) any later version. 10 * 11 * This library is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 14 * Lesser General Public License for more details. 15 * 16 * You should have received a copy of the GNU Lesser General Public 17 * License along with this library; if not, see 18 * <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qapi/error.h" 23 #include "qemu/module.h" 24 #include "hw/pci/msi.h" 25 #include "hw/pci/pci_bridge.h" 26 #include "hw/pci/pci_host.h" 27 #include "hw/pci/pcie_port.h" 28 #include "migration/vmstate.h" 29 #include "hw/irq.h" 30 #include "hw/pci-host/designware.h" 31 32 #define DESIGNWARE_PCIE_PORT_LINK_CONTROL 0x710 33 #define DESIGNWARE_PCIE_PHY_DEBUG_R1 0x72C 34 #define DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP BIT(4) 35 #define DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL 0x80C 36 #define DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE BIT(17) 37 #define DESIGNWARE_PCIE_MSI_ADDR_LO 0x820 38 #define DESIGNWARE_PCIE_MSI_ADDR_HI 0x824 39 #define DESIGNWARE_PCIE_MSI_INTR0_ENABLE 0x828 40 #define DESIGNWARE_PCIE_MSI_INTR0_MASK 0x82C 41 #define DESIGNWARE_PCIE_MSI_INTR0_STATUS 0x830 42 #define DESIGNWARE_PCIE_ATU_VIEWPORT 0x900 43 #define DESIGNWARE_PCIE_ATU_REGION_INBOUND BIT(31) 44 #define DESIGNWARE_PCIE_ATU_CR1 0x904 45 #define DESIGNWARE_PCIE_ATU_TYPE_MEM (0x0 << 0) 46 #define DESIGNWARE_PCIE_ATU_CR2 0x908 47 #define DESIGNWARE_PCIE_ATU_ENABLE BIT(31) 48 #define DESIGNWARE_PCIE_ATU_LOWER_BASE 0x90C 49 #define DESIGNWARE_PCIE_ATU_UPPER_BASE 0x910 50 #define DESIGNWARE_PCIE_ATU_LIMIT 0x914 51 #define DESIGNWARE_PCIE_ATU_LOWER_TARGET 0x918 52 #define DESIGNWARE_PCIE_ATU_BUS(x) (((x) >> 24) & 0xff) 53 #define DESIGNWARE_PCIE_ATU_DEVFN(x) (((x) >> 16) & 0xff) 54 #define DESIGNWARE_PCIE_ATU_UPPER_TARGET 0x91C 55 56 #define DESIGNWARE_PCIE_IRQ_MSI 3 57 58 static DesignwarePCIEHost * 59 designware_pcie_root_to_host(DesignwarePCIERoot *root) 60 { 61 BusState *bus = qdev_get_parent_bus(DEVICE(root)); 62 return DESIGNWARE_PCIE_HOST(bus->parent); 63 } 64 65 static void designware_pcie_root_msi_write(void *opaque, hwaddr addr, 66 uint64_t val, unsigned len) 67 { 68 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(opaque); 69 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); 70 71 root->msi.intr[0].status |= BIT(val) & root->msi.intr[0].enable; 72 73 if (root->msi.intr[0].status & ~root->msi.intr[0].mask) { 74 qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 1); 75 } 76 } 77 78 static const MemoryRegionOps designware_pci_host_msi_ops = { 79 .write = designware_pcie_root_msi_write, 80 .endianness = DEVICE_LITTLE_ENDIAN, 81 .valid = { 82 .min_access_size = 4, 83 .max_access_size = 4, 84 }, 85 }; 86 87 static void designware_pcie_root_update_msi_mapping(DesignwarePCIERoot *root) 88 89 { 90 MemoryRegion *mem = &root->msi.iomem; 91 const uint64_t base = root->msi.base; 92 const bool enable = root->msi.intr[0].enable; 93 94 memory_region_set_address(mem, base); 95 memory_region_set_enabled(mem, enable); 96 } 97 98 static DesignwarePCIEViewport * 99 designware_pcie_root_get_current_viewport(DesignwarePCIERoot *root) 100 { 101 const unsigned int idx = root->atu_viewport & 0xF; 102 const unsigned int dir = 103 !!(root->atu_viewport & DESIGNWARE_PCIE_ATU_REGION_INBOUND); 104 return &root->viewports[dir][idx]; 105 } 106 107 static uint32_t 108 designware_pcie_root_config_read(PCIDevice *d, uint32_t address, int len) 109 { 110 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); 111 DesignwarePCIEViewport *viewport = 112 designware_pcie_root_get_current_viewport(root); 113 114 uint32_t val; 115 116 switch (address) { 117 case DESIGNWARE_PCIE_PORT_LINK_CONTROL: 118 /* 119 * Linux guest uses this register only to configure number of 120 * PCIE lane (which in our case is irrelevant) and doesn't 121 * really care about the value it reads from this register 122 */ 123 val = 0xDEADBEEF; 124 break; 125 126 case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL: 127 /* 128 * To make sure that any code in guest waiting for speed 129 * change does not time out we always report 130 * PORT_LOGIC_SPEED_CHANGE as set 131 */ 132 val = DESIGNWARE_PCIE_PORT_LOGIC_SPEED_CHANGE; 133 break; 134 135 case DESIGNWARE_PCIE_MSI_ADDR_LO: 136 val = root->msi.base; 137 break; 138 139 case DESIGNWARE_PCIE_MSI_ADDR_HI: 140 val = root->msi.base >> 32; 141 break; 142 143 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: 144 val = root->msi.intr[0].enable; 145 break; 146 147 case DESIGNWARE_PCIE_MSI_INTR0_MASK: 148 val = root->msi.intr[0].mask; 149 break; 150 151 case DESIGNWARE_PCIE_MSI_INTR0_STATUS: 152 val = root->msi.intr[0].status; 153 break; 154 155 case DESIGNWARE_PCIE_PHY_DEBUG_R1: 156 val = DESIGNWARE_PCIE_PHY_DEBUG_R1_XMLH_LINK_UP; 157 break; 158 159 case DESIGNWARE_PCIE_ATU_VIEWPORT: 160 val = root->atu_viewport; 161 break; 162 163 case DESIGNWARE_PCIE_ATU_LOWER_BASE: 164 val = viewport->base; 165 break; 166 167 case DESIGNWARE_PCIE_ATU_UPPER_BASE: 168 val = viewport->base >> 32; 169 break; 170 171 case DESIGNWARE_PCIE_ATU_LOWER_TARGET: 172 val = viewport->target; 173 break; 174 175 case DESIGNWARE_PCIE_ATU_UPPER_TARGET: 176 val = viewport->target >> 32; 177 break; 178 179 case DESIGNWARE_PCIE_ATU_LIMIT: 180 val = viewport->limit; 181 break; 182 183 case DESIGNWARE_PCIE_ATU_CR1: 184 case DESIGNWARE_PCIE_ATU_CR2: /* FALLTHROUGH */ 185 val = viewport->cr[(address - DESIGNWARE_PCIE_ATU_CR1) / 186 sizeof(uint32_t)]; 187 break; 188 189 default: 190 val = pci_default_read_config(d, address, len); 191 break; 192 } 193 194 return val; 195 } 196 197 static uint64_t designware_pcie_root_data_access(void *opaque, hwaddr addr, 198 uint64_t *val, unsigned len) 199 { 200 DesignwarePCIEViewport *viewport = opaque; 201 DesignwarePCIERoot *root = viewport->root; 202 203 const uint8_t busnum = DESIGNWARE_PCIE_ATU_BUS(viewport->target); 204 const uint8_t devfn = DESIGNWARE_PCIE_ATU_DEVFN(viewport->target); 205 PCIBus *pcibus = pci_get_bus(PCI_DEVICE(root)); 206 PCIDevice *pcidev = pci_find_device(pcibus, busnum, devfn); 207 208 if (pcidev) { 209 addr &= pci_config_size(pcidev) - 1; 210 211 if (val) { 212 pci_host_config_write_common(pcidev, addr, 213 pci_config_size(pcidev), 214 *val, len); 215 } else { 216 return pci_host_config_read_common(pcidev, addr, 217 pci_config_size(pcidev), 218 len); 219 } 220 } 221 222 return UINT64_MAX; 223 } 224 225 static uint64_t designware_pcie_root_data_read(void *opaque, hwaddr addr, 226 unsigned len) 227 { 228 return designware_pcie_root_data_access(opaque, addr, NULL, len); 229 } 230 231 static void designware_pcie_root_data_write(void *opaque, hwaddr addr, 232 uint64_t val, unsigned len) 233 { 234 designware_pcie_root_data_access(opaque, addr, &val, len); 235 } 236 237 static const MemoryRegionOps designware_pci_host_conf_ops = { 238 .read = designware_pcie_root_data_read, 239 .write = designware_pcie_root_data_write, 240 .endianness = DEVICE_LITTLE_ENDIAN, 241 .valid = { 242 .min_access_size = 1, 243 .max_access_size = 4, 244 }, 245 }; 246 247 static void designware_pcie_update_viewport(DesignwarePCIERoot *root, 248 DesignwarePCIEViewport *viewport) 249 { 250 const uint64_t target = viewport->target; 251 const uint64_t base = viewport->base; 252 const uint64_t size = (uint64_t)viewport->limit - base + 1; 253 const bool enabled = viewport->cr[1] & DESIGNWARE_PCIE_ATU_ENABLE; 254 255 MemoryRegion *current, *other; 256 257 if (viewport->cr[0] == DESIGNWARE_PCIE_ATU_TYPE_MEM) { 258 current = &viewport->mem; 259 other = &viewport->cfg; 260 memory_region_set_alias_offset(current, target); 261 } else { 262 current = &viewport->cfg; 263 other = &viewport->mem; 264 } 265 266 /* 267 * An outbound viewport can be reconfigure from being MEM to CFG, 268 * to account for that we disable the "other" memory region that 269 * becomes unused due to that fact. 270 */ 271 memory_region_set_enabled(other, false); 272 if (enabled) { 273 memory_region_set_size(current, size); 274 memory_region_set_address(current, base); 275 } 276 memory_region_set_enabled(current, enabled); 277 } 278 279 static void designware_pcie_root_config_write(PCIDevice *d, uint32_t address, 280 uint32_t val, int len) 281 { 282 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(d); 283 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); 284 DesignwarePCIEViewport *viewport = 285 designware_pcie_root_get_current_viewport(root); 286 287 switch (address) { 288 case DESIGNWARE_PCIE_PORT_LINK_CONTROL: 289 case DESIGNWARE_PCIE_LINK_WIDTH_SPEED_CONTROL: 290 case DESIGNWARE_PCIE_PHY_DEBUG_R1: 291 /* No-op */ 292 break; 293 294 case DESIGNWARE_PCIE_MSI_ADDR_LO: 295 root->msi.base &= 0xFFFFFFFF00000000ULL; 296 root->msi.base |= val; 297 designware_pcie_root_update_msi_mapping(root); 298 break; 299 300 case DESIGNWARE_PCIE_MSI_ADDR_HI: 301 root->msi.base &= 0x00000000FFFFFFFFULL; 302 root->msi.base |= (uint64_t)val << 32; 303 designware_pcie_root_update_msi_mapping(root); 304 break; 305 306 case DESIGNWARE_PCIE_MSI_INTR0_ENABLE: 307 root->msi.intr[0].enable = val; 308 designware_pcie_root_update_msi_mapping(root); 309 break; 310 311 case DESIGNWARE_PCIE_MSI_INTR0_MASK: 312 root->msi.intr[0].mask = val; 313 break; 314 315 case DESIGNWARE_PCIE_MSI_INTR0_STATUS: 316 root->msi.intr[0].status ^= val; 317 if (!root->msi.intr[0].status) { 318 qemu_set_irq(host->pci.irqs[DESIGNWARE_PCIE_IRQ_MSI], 0); 319 } 320 break; 321 322 case DESIGNWARE_PCIE_ATU_VIEWPORT: 323 root->atu_viewport = val; 324 break; 325 326 case DESIGNWARE_PCIE_ATU_LOWER_BASE: 327 viewport->base &= 0xFFFFFFFF00000000ULL; 328 viewport->base |= val; 329 break; 330 331 case DESIGNWARE_PCIE_ATU_UPPER_BASE: 332 viewport->base &= 0x00000000FFFFFFFFULL; 333 viewport->base |= (uint64_t)val << 32; 334 break; 335 336 case DESIGNWARE_PCIE_ATU_LOWER_TARGET: 337 viewport->target &= 0xFFFFFFFF00000000ULL; 338 viewport->target |= val; 339 break; 340 341 case DESIGNWARE_PCIE_ATU_UPPER_TARGET: 342 viewport->target &= 0x00000000FFFFFFFFULL; 343 viewport->target |= val; 344 break; 345 346 case DESIGNWARE_PCIE_ATU_LIMIT: 347 viewport->limit = val; 348 break; 349 350 case DESIGNWARE_PCIE_ATU_CR1: 351 viewport->cr[0] = val; 352 break; 353 case DESIGNWARE_PCIE_ATU_CR2: 354 viewport->cr[1] = val; 355 designware_pcie_update_viewport(root, viewport); 356 break; 357 358 default: 359 pci_bridge_write_config(d, address, val, len); 360 break; 361 } 362 } 363 364 static char *designware_pcie_viewport_name(const char *direction, 365 unsigned int i, 366 const char *type) 367 { 368 return g_strdup_printf("PCI %s Viewport %u [%s]", 369 direction, i, type); 370 } 371 372 static void designware_pcie_root_realize(PCIDevice *dev, Error **errp) 373 { 374 DesignwarePCIERoot *root = DESIGNWARE_PCIE_ROOT(dev); 375 DesignwarePCIEHost *host = designware_pcie_root_to_host(root); 376 MemoryRegion *address_space = &host->pci.memory; 377 PCIBridge *br = PCI_BRIDGE(dev); 378 DesignwarePCIEViewport *viewport; 379 /* 380 * Dummy values used for initial configuration of MemoryRegions 381 * that belong to a given viewport 382 */ 383 const hwaddr dummy_offset = 0; 384 const uint64_t dummy_size = 4; 385 size_t i; 386 387 br->bus_name = "dw-pcie"; 388 389 pci_set_word(dev->config + PCI_COMMAND, 390 PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); 391 392 pci_config_set_interrupt_pin(dev->config, 1); 393 pci_bridge_initfn(dev, TYPE_PCIE_BUS); 394 395 pcie_port_init_reg(dev); 396 397 pcie_cap_init(dev, 0x70, PCI_EXP_TYPE_ROOT_PORT, 398 0, &error_fatal); 399 400 msi_nonbroken = true; 401 msi_init(dev, 0x50, 32, true, true, &error_fatal); 402 403 for (i = 0; i < DESIGNWARE_PCIE_NUM_VIEWPORTS; i++) { 404 MemoryRegion *source, *destination, *mem; 405 const char *direction; 406 char *name; 407 408 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][i]; 409 viewport->inbound = true; 410 viewport->base = 0x0000000000000000ULL; 411 viewport->target = 0x0000000000000000ULL; 412 viewport->limit = UINT32_MAX; 413 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; 414 415 source = &host->pci.address_space_root; 416 destination = get_system_memory(); 417 direction = "Inbound"; 418 419 /* 420 * Configure MemoryRegion implementing PCI -> CPU memory 421 * access 422 */ 423 mem = &viewport->mem; 424 name = designware_pcie_viewport_name(direction, i, "MEM"); 425 memory_region_init_alias(mem, OBJECT(root), name, destination, 426 dummy_offset, dummy_size); 427 memory_region_add_subregion_overlap(source, dummy_offset, mem, -1); 428 memory_region_set_enabled(mem, false); 429 g_free(name); 430 431 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_OUTBOUND][i]; 432 viewport->root = root; 433 viewport->inbound = false; 434 viewport->base = 0x0000000000000000ULL; 435 viewport->target = 0x0000000000000000ULL; 436 viewport->limit = UINT32_MAX; 437 viewport->cr[0] = DESIGNWARE_PCIE_ATU_TYPE_MEM; 438 439 destination = &host->pci.memory; 440 direction = "Outbound"; 441 source = get_system_memory(); 442 443 /* 444 * Configure MemoryRegion implementing CPU -> PCI memory 445 * access 446 */ 447 mem = &viewport->mem; 448 name = designware_pcie_viewport_name(direction, i, "MEM"); 449 memory_region_init_alias(mem, OBJECT(root), name, destination, 450 dummy_offset, dummy_size); 451 memory_region_add_subregion(source, dummy_offset, mem); 452 memory_region_set_enabled(mem, false); 453 g_free(name); 454 455 /* 456 * Configure MemoryRegion implementing access to configuration 457 * space 458 */ 459 mem = &viewport->cfg; 460 name = designware_pcie_viewport_name(direction, i, "CFG"); 461 memory_region_init_io(&viewport->cfg, OBJECT(root), 462 &designware_pci_host_conf_ops, 463 viewport, name, dummy_size); 464 memory_region_add_subregion(source, dummy_offset, mem); 465 memory_region_set_enabled(mem, false); 466 g_free(name); 467 } 468 469 /* 470 * If no inbound iATU windows are configured, HW defaults to 471 * letting inbound TLPs to pass in. We emulate that by exlicitly 472 * configuring first inbound window to cover all of target's 473 * address space. 474 * 475 * NOTE: This will not work correctly for the case when first 476 * configured inbound window is window 0 477 */ 478 viewport = &root->viewports[DESIGNWARE_PCIE_VIEWPORT_INBOUND][0]; 479 viewport->cr[1] = DESIGNWARE_PCIE_ATU_ENABLE; 480 designware_pcie_update_viewport(root, viewport); 481 482 memory_region_init_io(&root->msi.iomem, OBJECT(root), 483 &designware_pci_host_msi_ops, 484 root, "pcie-msi", 0x4); 485 /* 486 * We initially place MSI interrupt I/O region a adress 0 and 487 * disable it. It'll be later moved to correct offset and enabled 488 * in designware_pcie_root_update_msi_mapping() as a part of 489 * initialization done by guest OS 490 */ 491 memory_region_add_subregion(address_space, dummy_offset, &root->msi.iomem); 492 memory_region_set_enabled(&root->msi.iomem, false); 493 } 494 495 static void designware_pcie_set_irq(void *opaque, int irq_num, int level) 496 { 497 DesignwarePCIEHost *host = DESIGNWARE_PCIE_HOST(opaque); 498 499 qemu_set_irq(host->pci.irqs[irq_num], level); 500 } 501 502 static const char * 503 designware_pcie_host_root_bus_path(PCIHostState *host_bridge, PCIBus *rootbus) 504 { 505 return "0000:00"; 506 } 507 508 static const VMStateDescription vmstate_designware_pcie_msi_bank = { 509 .name = "designware-pcie-msi-bank", 510 .version_id = 1, 511 .minimum_version_id = 1, 512 .fields = (VMStateField[]) { 513 VMSTATE_UINT32(enable, DesignwarePCIEMSIBank), 514 VMSTATE_UINT32(mask, DesignwarePCIEMSIBank), 515 VMSTATE_UINT32(status, DesignwarePCIEMSIBank), 516 VMSTATE_END_OF_LIST() 517 } 518 }; 519 520 static const VMStateDescription vmstate_designware_pcie_msi = { 521 .name = "designware-pcie-msi", 522 .version_id = 1, 523 .minimum_version_id = 1, 524 .fields = (VMStateField[]) { 525 VMSTATE_UINT64(base, DesignwarePCIEMSI), 526 VMSTATE_STRUCT_ARRAY(intr, 527 DesignwarePCIEMSI, 528 DESIGNWARE_PCIE_NUM_MSI_BANKS, 529 1, 530 vmstate_designware_pcie_msi_bank, 531 DesignwarePCIEMSIBank), 532 VMSTATE_END_OF_LIST() 533 } 534 }; 535 536 static const VMStateDescription vmstate_designware_pcie_viewport = { 537 .name = "designware-pcie-viewport", 538 .version_id = 1, 539 .minimum_version_id = 1, 540 .fields = (VMStateField[]) { 541 VMSTATE_UINT64(base, DesignwarePCIEViewport), 542 VMSTATE_UINT64(target, DesignwarePCIEViewport), 543 VMSTATE_UINT32(limit, DesignwarePCIEViewport), 544 VMSTATE_UINT32_ARRAY(cr, DesignwarePCIEViewport, 2), 545 VMSTATE_END_OF_LIST() 546 } 547 }; 548 549 static const VMStateDescription vmstate_designware_pcie_root = { 550 .name = "designware-pcie-root", 551 .version_id = 1, 552 .minimum_version_id = 1, 553 .fields = (VMStateField[]) { 554 VMSTATE_PCI_DEVICE(parent_obj, PCIBridge), 555 VMSTATE_UINT32(atu_viewport, DesignwarePCIERoot), 556 VMSTATE_STRUCT_2DARRAY(viewports, 557 DesignwarePCIERoot, 558 2, 559 DESIGNWARE_PCIE_NUM_VIEWPORTS, 560 1, 561 vmstate_designware_pcie_viewport, 562 DesignwarePCIEViewport), 563 VMSTATE_STRUCT(msi, 564 DesignwarePCIERoot, 565 1, 566 vmstate_designware_pcie_msi, 567 DesignwarePCIEMSI), 568 VMSTATE_END_OF_LIST() 569 } 570 }; 571 572 static void designware_pcie_root_class_init(ObjectClass *klass, void *data) 573 { 574 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 575 DeviceClass *dc = DEVICE_CLASS(klass); 576 577 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 578 579 k->vendor_id = PCI_VENDOR_ID_SYNOPSYS; 580 k->device_id = 0xABCD; 581 k->revision = 0; 582 k->class_id = PCI_CLASS_BRIDGE_PCI; 583 k->is_bridge = true; 584 k->exit = pci_bridge_exitfn; 585 k->realize = designware_pcie_root_realize; 586 k->config_read = designware_pcie_root_config_read; 587 k->config_write = designware_pcie_root_config_write; 588 589 dc->reset = pci_bridge_reset; 590 /* 591 * PCI-facing part of the host bridge, not usable without the 592 * host-facing part, which can't be device_add'ed, yet. 593 */ 594 dc->user_creatable = false; 595 dc->vmsd = &vmstate_designware_pcie_root; 596 } 597 598 static uint64_t designware_pcie_host_mmio_read(void *opaque, hwaddr addr, 599 unsigned int size) 600 { 601 PCIHostState *pci = PCI_HOST_BRIDGE(opaque); 602 PCIDevice *device = pci_find_device(pci->bus, 0, 0); 603 604 return pci_host_config_read_common(device, 605 addr, 606 pci_config_size(device), 607 size); 608 } 609 610 static void designware_pcie_host_mmio_write(void *opaque, hwaddr addr, 611 uint64_t val, unsigned int size) 612 { 613 PCIHostState *pci = PCI_HOST_BRIDGE(opaque); 614 PCIDevice *device = pci_find_device(pci->bus, 0, 0); 615 616 return pci_host_config_write_common(device, 617 addr, 618 pci_config_size(device), 619 val, size); 620 } 621 622 static const MemoryRegionOps designware_pci_mmio_ops = { 623 .read = designware_pcie_host_mmio_read, 624 .write = designware_pcie_host_mmio_write, 625 .endianness = DEVICE_LITTLE_ENDIAN, 626 .impl = { 627 /* 628 * Our device would not work correctly if the guest was doing 629 * unaligned access. This might not be a limitation on the real 630 * device but in practice there is no reason for a guest to access 631 * this device unaligned. 632 */ 633 .min_access_size = 4, 634 .max_access_size = 4, 635 .unaligned = false, 636 }, 637 }; 638 639 static AddressSpace *designware_pcie_host_set_iommu(PCIBus *bus, void *opaque, 640 int devfn) 641 { 642 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(opaque); 643 644 return &s->pci.address_space; 645 } 646 647 static void designware_pcie_host_realize(DeviceState *dev, Error **errp) 648 { 649 PCIHostState *pci = PCI_HOST_BRIDGE(dev); 650 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(dev); 651 SysBusDevice *sbd = SYS_BUS_DEVICE(dev); 652 size_t i; 653 654 for (i = 0; i < ARRAY_SIZE(s->pci.irqs); i++) { 655 sysbus_init_irq(sbd, &s->pci.irqs[i]); 656 } 657 658 memory_region_init_io(&s->mmio, 659 OBJECT(s), 660 &designware_pci_mmio_ops, 661 s, 662 "pcie.reg", 4 * 1024); 663 sysbus_init_mmio(sbd, &s->mmio); 664 665 memory_region_init(&s->pci.io, OBJECT(s), "pcie-pio", 16); 666 memory_region_init(&s->pci.memory, OBJECT(s), 667 "pcie-bus-memory", 668 UINT64_MAX); 669 670 pci->bus = pci_register_root_bus(dev, "pcie", 671 designware_pcie_set_irq, 672 pci_swizzle_map_irq_fn, 673 s, 674 &s->pci.memory, 675 &s->pci.io, 676 0, 4, 677 TYPE_PCIE_BUS); 678 679 memory_region_init(&s->pci.address_space_root, 680 OBJECT(s), 681 "pcie-bus-address-space-root", 682 UINT64_MAX); 683 memory_region_add_subregion(&s->pci.address_space_root, 684 0x0, &s->pci.memory); 685 address_space_init(&s->pci.address_space, 686 &s->pci.address_space_root, 687 "pcie-bus-address-space"); 688 pci_setup_iommu(pci->bus, designware_pcie_host_set_iommu, s); 689 690 qdev_set_parent_bus(DEVICE(&s->root), BUS(pci->bus)); 691 qdev_init_nofail(DEVICE(&s->root)); 692 } 693 694 static const VMStateDescription vmstate_designware_pcie_host = { 695 .name = "designware-pcie-host", 696 .version_id = 1, 697 .minimum_version_id = 1, 698 .fields = (VMStateField[]) { 699 VMSTATE_STRUCT(root, 700 DesignwarePCIEHost, 701 1, 702 vmstate_designware_pcie_root, 703 DesignwarePCIERoot), 704 VMSTATE_END_OF_LIST() 705 } 706 }; 707 708 static void designware_pcie_host_class_init(ObjectClass *klass, void *data) 709 { 710 DeviceClass *dc = DEVICE_CLASS(klass); 711 PCIHostBridgeClass *hc = PCI_HOST_BRIDGE_CLASS(klass); 712 713 hc->root_bus_path = designware_pcie_host_root_bus_path; 714 dc->realize = designware_pcie_host_realize; 715 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 716 dc->fw_name = "pci"; 717 dc->vmsd = &vmstate_designware_pcie_host; 718 } 719 720 static void designware_pcie_host_init(Object *obj) 721 { 722 DesignwarePCIEHost *s = DESIGNWARE_PCIE_HOST(obj); 723 DesignwarePCIERoot *root = &s->root; 724 725 object_initialize_child(obj, "root", root, sizeof(*root), 726 TYPE_DESIGNWARE_PCIE_ROOT, &error_abort, NULL); 727 qdev_prop_set_int32(DEVICE(root), "addr", PCI_DEVFN(0, 0)); 728 qdev_prop_set_bit(DEVICE(root), "multifunction", false); 729 } 730 731 static const TypeInfo designware_pcie_root_info = { 732 .name = TYPE_DESIGNWARE_PCIE_ROOT, 733 .parent = TYPE_PCI_BRIDGE, 734 .instance_size = sizeof(DesignwarePCIERoot), 735 .class_init = designware_pcie_root_class_init, 736 .interfaces = (InterfaceInfo[]) { 737 { INTERFACE_PCIE_DEVICE }, 738 { } 739 }, 740 }; 741 742 static const TypeInfo designware_pcie_host_info = { 743 .name = TYPE_DESIGNWARE_PCIE_HOST, 744 .parent = TYPE_PCI_HOST_BRIDGE, 745 .instance_size = sizeof(DesignwarePCIEHost), 746 .instance_init = designware_pcie_host_init, 747 .class_init = designware_pcie_host_class_init, 748 }; 749 750 static void designware_pcie_register(void) 751 { 752 type_register_static(&designware_pcie_root_info); 753 type_register_static(&designware_pcie_host_info); 754 } 755 type_init(designware_pcie_register) 756