1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * fulong 2e mini pc has a bonito north bridge. 15 */ 16 17 /* 18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 19 * 20 * devfn pci_slot<<3 + funno 21 * one pci bus can have 32 devices and each device can have 8 functions. 22 * 23 * In bonito north bridge, pci slot = IDSEL bit - 12. 24 * For example, PCI_IDSEL_VIA686B = 17, 25 * pci slot = 17-12=5 26 * 27 * so 28 * VT686B_FUN0's devfn = (5<<3)+0 29 * VT686B_FUN1's devfn = (5<<3)+1 30 * 31 * qemu also uses pci address for north bridge to access pci config register. 32 * bus_no [23:16] 33 * dev_no [15:11] 34 * fun_no [10:8] 35 * reg_no [7:2] 36 * 37 * so function bonito_sbridge_pciaddr for the translation from 38 * north bridge address to pci address. 39 */ 40 41 #include "qemu/osdep.h" 42 #include "qemu/error-report.h" 43 #include "hw/pci/pci.h" 44 #include "hw/i386/pc.h" 45 #include "hw/irq.h" 46 #include "hw/mips/mips.h" 47 #include "hw/pci/pci_host.h" 48 #include "migration/vmstate.h" 49 #include "sysemu/reset.h" 50 #include "sysemu/runstate.h" 51 #include "exec/address-spaces.h" 52 53 /* #define DEBUG_BONITO */ 54 55 #ifdef DEBUG_BONITO 56 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) 57 #else 58 #define DPRINTF(fmt, ...) 59 #endif 60 61 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 62 #define BONITO_BOOT_BASE 0x1fc00000 63 #define BONITO_BOOT_SIZE 0x00100000 64 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1) 65 #define BONITO_FLASH_BASE 0x1c000000 66 #define BONITO_FLASH_SIZE 0x03000000 67 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1) 68 #define BONITO_SOCKET_BASE 0x1f800000 69 #define BONITO_SOCKET_SIZE 0x00400000 70 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1) 71 #define BONITO_REG_BASE 0x1fe00000 72 #define BONITO_REG_SIZE 0x00040000 73 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1) 74 #define BONITO_DEV_BASE 0x1ff00000 75 #define BONITO_DEV_SIZE 0x00100000 76 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1) 77 #define BONITO_PCILO_BASE 0x10000000 78 #define BONITO_PCILO_BASE_VA 0xb0000000 79 #define BONITO_PCILO_SIZE 0x0c000000 80 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1) 81 #define BONITO_PCILO0_BASE 0x10000000 82 #define BONITO_PCILO1_BASE 0x14000000 83 #define BONITO_PCILO2_BASE 0x18000000 84 #define BONITO_PCIHI_BASE 0x20000000 85 #define BONITO_PCIHI_SIZE 0x20000000 86 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1) 87 #define BONITO_PCIIO_BASE 0x1fd00000 88 #define BONITO_PCIIO_BASE_VA 0xbfd00000 89 #define BONITO_PCIIO_SIZE 0x00010000 90 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1) 91 #define BONITO_PCICFG_BASE 0x1fe80000 92 #define BONITO_PCICFG_SIZE 0x00080000 93 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1) 94 95 96 #define BONITO_PCICONFIGBASE 0x00 97 #define BONITO_REGBASE 0x100 98 99 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE) 100 #define BONITO_PCICONFIG_SIZE (0x100) 101 102 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE) 103 #define BONITO_INTERNAL_REG_SIZE (0x70) 104 105 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 106 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 107 108 109 110 /* 1. Bonito h/w Configuration */ 111 /* Power on register */ 112 113 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 114 #define BONITO_BONGENCFG_OFFSET 0x4 115 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */ 116 117 /* 2. IO & IDE configuration */ 118 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 119 120 /* 3. IO & IDE configuration */ 121 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 122 123 /* 4. PCI address map control */ 124 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 125 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 126 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 127 128 /* 5. ICU & GPIO regs */ 129 /* GPIO Regs - r/w */ 130 #define BONITO_GPIODATA_OFFSET 0x1c 131 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 132 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 133 134 /* ICU Configuration Regs - r/w */ 135 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 136 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 137 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 138 139 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 140 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 141 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 142 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 143 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 144 145 /* PCI mail boxes */ 146 #define BONITO_PCIMAIL0_OFFSET 0x40 147 #define BONITO_PCIMAIL1_OFFSET 0x44 148 #define BONITO_PCIMAIL2_OFFSET 0x48 149 #define BONITO_PCIMAIL3_OFFSET 0x4c 150 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 151 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 152 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 153 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 154 155 /* 6. PCI cache */ 156 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 157 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 158 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 159 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 160 161 /* 7. other*/ 162 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 163 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 164 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 165 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 166 167 #define BONITO_REGS (0x70 >> 2) 168 169 /* PCI config for south bridge. type 0 */ 170 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 171 #define BONITO_PCICONF_IDSEL_OFFSET 11 172 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 173 #define BONITO_PCICONF_FUN_OFFSET 8 174 #define BONITO_PCICONF_REG_MASK 0xFC 175 #define BONITO_PCICONF_REG_OFFSET 0 176 177 178 /* idsel BIT = pci slot number +12 */ 179 #define PCI_SLOT_BASE 12 180 #define PCI_IDSEL_VIA686B_BIT (17) 181 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT) 182 183 #define PCI_ADDR(busno , devno , funno , regno) \ 184 ((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \ 185 (((funno) << 8) & 0x700) + (regno)) 186 187 typedef struct BonitoState BonitoState; 188 189 typedef struct PCIBonitoState { 190 PCIDevice dev; 191 192 BonitoState *pcihost; 193 uint32_t regs[BONITO_REGS]; 194 195 struct bonldma { 196 uint32_t ldmactrl; 197 uint32_t ldmastat; 198 uint32_t ldmaaddr; 199 uint32_t ldmago; 200 } bonldma; 201 202 /* Based at 1fe00300, bonito Copier */ 203 struct boncop { 204 uint32_t copctrl; 205 uint32_t copstat; 206 uint32_t coppaddr; 207 uint32_t copgo; 208 } boncop; 209 210 /* Bonito registers */ 211 MemoryRegion iomem; 212 MemoryRegion iomem_ldma; 213 MemoryRegion iomem_cop; 214 MemoryRegion bonito_pciio; 215 MemoryRegion bonito_localio; 216 217 } PCIBonitoState; 218 219 struct BonitoState { 220 PCIHostState parent_obj; 221 qemu_irq *pic; 222 PCIBonitoState *pci_dev; 223 MemoryRegion pci_mem; 224 }; 225 226 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" 227 #define BONITO_PCI_HOST_BRIDGE(obj) \ 228 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) 229 230 #define TYPE_PCI_BONITO "Bonito" 231 #define PCI_BONITO(obj) \ 232 OBJECT_CHECK(PCIBonitoState, (obj), TYPE_PCI_BONITO) 233 234 static void bonito_writel(void *opaque, hwaddr addr, 235 uint64_t val, unsigned size) 236 { 237 PCIBonitoState *s = opaque; 238 uint32_t saddr; 239 int reset = 0; 240 241 saddr = addr >> 2; 242 243 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", 244 addr, val, saddr); 245 switch (saddr) { 246 case BONITO_BONPONCFG: 247 case BONITO_IODEVCFG: 248 case BONITO_SDCFG: 249 case BONITO_PCIMAP: 250 case BONITO_PCIMEMBASECFG: 251 case BONITO_PCIMAP_CFG: 252 case BONITO_GPIODATA: 253 case BONITO_GPIOIE: 254 case BONITO_INTEDGE: 255 case BONITO_INTSTEER: 256 case BONITO_INTPOL: 257 case BONITO_PCIMAIL0: 258 case BONITO_PCIMAIL1: 259 case BONITO_PCIMAIL2: 260 case BONITO_PCIMAIL3: 261 case BONITO_PCICACHECTRL: 262 case BONITO_PCICACHETAG: 263 case BONITO_PCIBADADDR: 264 case BONITO_PCIMSTAT: 265 case BONITO_TIMECFG: 266 case BONITO_CPUCFG: 267 case BONITO_DQCFG: 268 case BONITO_MEMSIZE: 269 s->regs[saddr] = val; 270 break; 271 case BONITO_BONGENCFG: 272 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 273 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 274 } 275 s->regs[saddr] = val; 276 if (reset) { 277 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 278 } 279 break; 280 case BONITO_INTENSET: 281 s->regs[BONITO_INTENSET] = val; 282 s->regs[BONITO_INTEN] |= val; 283 break; 284 case BONITO_INTENCLR: 285 s->regs[BONITO_INTENCLR] = val; 286 s->regs[BONITO_INTEN] &= ~val; 287 break; 288 case BONITO_INTEN: 289 case BONITO_INTISR: 290 DPRINTF("write to readonly bonito register %x\n", saddr); 291 break; 292 default: 293 DPRINTF("write to unknown bonito register %x\n", saddr); 294 break; 295 } 296 } 297 298 static uint64_t bonito_readl(void *opaque, hwaddr addr, 299 unsigned size) 300 { 301 PCIBonitoState *s = opaque; 302 uint32_t saddr; 303 304 saddr = addr >> 2; 305 306 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 307 switch (saddr) { 308 case BONITO_INTISR: 309 return s->regs[saddr]; 310 default: 311 return s->regs[saddr]; 312 } 313 } 314 315 static const MemoryRegionOps bonito_ops = { 316 .read = bonito_readl, 317 .write = bonito_writel, 318 .endianness = DEVICE_NATIVE_ENDIAN, 319 .valid = { 320 .min_access_size = 4, 321 .max_access_size = 4, 322 }, 323 }; 324 325 static void bonito_pciconf_writel(void *opaque, hwaddr addr, 326 uint64_t val, unsigned size) 327 { 328 PCIBonitoState *s = opaque; 329 PCIDevice *d = PCI_DEVICE(s); 330 331 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 332 d->config_write(d, addr, val, 4); 333 } 334 335 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, 336 unsigned size) 337 { 338 339 PCIBonitoState *s = opaque; 340 PCIDevice *d = PCI_DEVICE(s); 341 342 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 343 return d->config_read(d, addr, 4); 344 } 345 346 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 347 348 static const MemoryRegionOps bonito_pciconf_ops = { 349 .read = bonito_pciconf_readl, 350 .write = bonito_pciconf_writel, 351 .endianness = DEVICE_NATIVE_ENDIAN, 352 .valid = { 353 .min_access_size = 4, 354 .max_access_size = 4, 355 }, 356 }; 357 358 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, 359 unsigned size) 360 { 361 uint32_t val; 362 PCIBonitoState *s = opaque; 363 364 if (addr >= sizeof(s->bonldma)) { 365 return 0; 366 } 367 368 val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)]; 369 370 return val; 371 } 372 373 static void bonito_ldma_writel(void *opaque, hwaddr addr, 374 uint64_t val, unsigned size) 375 { 376 PCIBonitoState *s = opaque; 377 378 if (addr >= sizeof(s->bonldma)) { 379 return; 380 } 381 382 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff; 383 } 384 385 static const MemoryRegionOps bonito_ldma_ops = { 386 .read = bonito_ldma_readl, 387 .write = bonito_ldma_writel, 388 .endianness = DEVICE_NATIVE_ENDIAN, 389 .valid = { 390 .min_access_size = 4, 391 .max_access_size = 4, 392 }, 393 }; 394 395 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, 396 unsigned size) 397 { 398 uint32_t val; 399 PCIBonitoState *s = opaque; 400 401 if (addr >= sizeof(s->boncop)) { 402 return 0; 403 } 404 405 val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)]; 406 407 return val; 408 } 409 410 static void bonito_cop_writel(void *opaque, hwaddr addr, 411 uint64_t val, unsigned size) 412 { 413 PCIBonitoState *s = opaque; 414 415 if (addr >= sizeof(s->boncop)) { 416 return; 417 } 418 419 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff; 420 } 421 422 static const MemoryRegionOps bonito_cop_ops = { 423 .read = bonito_cop_readl, 424 .write = bonito_cop_writel, 425 .endianness = DEVICE_NATIVE_ENDIAN, 426 .valid = { 427 .min_access_size = 4, 428 .max_access_size = 4, 429 }, 430 }; 431 432 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) 433 { 434 PCIBonitoState *s = opaque; 435 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 436 uint32_t cfgaddr; 437 uint32_t idsel; 438 uint32_t devno; 439 uint32_t funno; 440 uint32_t regno; 441 uint32_t pciaddr; 442 443 /* support type0 pci config */ 444 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 445 return 0xffffffff; 446 } 447 448 cfgaddr = addr & 0xffff; 449 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 450 451 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> 452 BONITO_PCICONF_IDSEL_OFFSET; 453 devno = ctz32(idsel); 454 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 455 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 456 457 if (idsel == 0) { 458 error_report("error in bonito pci config address " TARGET_FMT_plx 459 ",pcimap_cfg=%x", addr, s->regs[BONITO_PCIMAP_CFG]); 460 exit(1); 461 } 462 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); 463 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 464 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); 465 466 return pciaddr; 467 } 468 469 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, 470 unsigned size) 471 { 472 PCIBonitoState *s = opaque; 473 PCIDevice *d = PCI_DEVICE(s); 474 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 475 uint32_t pciaddr; 476 uint16_t status; 477 478 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %x\n", 479 addr, size, val); 480 481 pciaddr = bonito_sbridge_pciaddr(s, addr); 482 483 if (pciaddr == 0xffffffff) { 484 return; 485 } 486 487 /* set the pci address in s->config_reg */ 488 phb->config_reg = (pciaddr) | (1u << 31); 489 pci_data_write(phb->bus, phb->config_reg, val, size); 490 491 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 492 status = pci_get_word(d->config + PCI_STATUS); 493 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 494 pci_set_word(d->config + PCI_STATUS, status); 495 } 496 497 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) 498 { 499 PCIBonitoState *s = opaque; 500 PCIDevice *d = PCI_DEVICE(s); 501 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 502 uint32_t pciaddr; 503 uint16_t status; 504 505 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); 506 507 pciaddr = bonito_sbridge_pciaddr(s, addr); 508 509 if (pciaddr == 0xffffffff) { 510 return MAKE_64BIT_MASK(0, size * 8); 511 } 512 513 /* set the pci address in s->config_reg */ 514 phb->config_reg = (pciaddr) | (1u << 31); 515 516 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 517 status = pci_get_word(d->config + PCI_STATUS); 518 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 519 pci_set_word(d->config + PCI_STATUS, status); 520 521 return pci_data_read(phb->bus, phb->config_reg, size); 522 } 523 524 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 525 static const MemoryRegionOps bonito_spciconf_ops = { 526 .read = bonito_spciconf_read, 527 .write = bonito_spciconf_write, 528 .valid.min_access_size = 1, 529 .valid.max_access_size = 4, 530 .impl.min_access_size = 1, 531 .impl.max_access_size = 4, 532 .endianness = DEVICE_NATIVE_ENDIAN, 533 }; 534 535 #define BONITO_IRQ_BASE 32 536 537 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 538 { 539 BonitoState *s = opaque; 540 qemu_irq *pic = s->pic; 541 PCIBonitoState *bonito_state = s->pci_dev; 542 int internal_irq = irq_num - BONITO_IRQ_BASE; 543 544 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { 545 qemu_irq_pulse(*pic); 546 } else { /* level triggered */ 547 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { 548 qemu_irq_raise(*pic); 549 } else { 550 qemu_irq_lower(*pic); 551 } 552 } 553 } 554 555 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 556 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) 557 { 558 int slot; 559 560 slot = (pci_dev->devfn >> 3); 561 562 switch (slot) { 563 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 564 return irq_num % 4 + BONITO_IRQ_BASE; 565 case 6: /* FULONG2E_ATI_SLOT, VGA */ 566 return 4 + BONITO_IRQ_BASE; 567 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ 568 return 5 + BONITO_IRQ_BASE; 569 case 8 ... 12: /* PCI slot 1 to 4 */ 570 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 571 default: /* Unknown device, don't do any translation */ 572 return irq_num; 573 } 574 } 575 576 static void bonito_reset(void *opaque) 577 { 578 PCIBonitoState *s = opaque; 579 580 /* set the default value of north bridge registers */ 581 582 s->regs[BONITO_BONPONCFG] = 0xc40; 583 s->regs[BONITO_BONGENCFG] = 0x1384; 584 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 585 s->regs[BONITO_SDCFG] = 0x255e0091; 586 587 s->regs[BONITO_GPIODATA] = 0x1ff; 588 s->regs[BONITO_GPIOIE] = 0x1ff; 589 s->regs[BONITO_DQCFG] = 0x8; 590 s->regs[BONITO_MEMSIZE] = 0x10000000; 591 s->regs[BONITO_PCIMAP] = 0x6140; 592 } 593 594 static const VMStateDescription vmstate_bonito = { 595 .name = "Bonito", 596 .version_id = 1, 597 .minimum_version_id = 1, 598 .fields = (VMStateField[]) { 599 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 600 VMSTATE_END_OF_LIST() 601 } 602 }; 603 604 static void bonito_pcihost_realize(DeviceState *dev, Error **errp) 605 { 606 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 607 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); 608 609 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCILO_SIZE); 610 phb->bus = pci_register_root_bus(DEVICE(dev), "pci", 611 pci_bonito_set_irq, pci_bonito_map_irq, 612 dev, &bs->pci_mem, get_system_io(), 613 0x28, 32, TYPE_PCI_BUS); 614 memory_region_add_subregion(get_system_memory(), BONITO_PCILO_BASE, 615 &bs->pci_mem); 616 } 617 618 static void bonito_realize(PCIDevice *dev, Error **errp) 619 { 620 PCIBonitoState *s = PCI_BONITO(dev); 621 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); 622 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 623 624 /* 625 * Bonito North Bridge, built on FPGA, 626 * VENDOR_ID/DEVICE_ID are "undefined" 627 */ 628 pci_config_set_prog_interface(dev->config, 0x00); 629 630 /* set the north bridge register mapping */ 631 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, 632 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 633 sysbus_init_mmio(sysbus, &s->iomem); 634 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 635 636 /* set the north bridge pci configure mapping */ 637 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, 638 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 639 sysbus_init_mmio(sysbus, &phb->conf_mem); 640 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 641 642 /* set the south bridge pci configure mapping */ 643 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, 644 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 645 sysbus_init_mmio(sysbus, &phb->data_mem); 646 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 647 648 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, 649 "ldma", 0x100); 650 sysbus_init_mmio(sysbus, &s->iomem_ldma); 651 sysbus_mmio_map(sysbus, 3, 0xbfe00200); 652 653 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, 654 "cop", 0x100); 655 sysbus_init_mmio(sysbus, &s->iomem_cop); 656 sysbus_mmio_map(sysbus, 4, 0xbfe00300); 657 658 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 659 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", 660 get_system_io(), 0, BONITO_PCIIO_SIZE); 661 sysbus_init_mmio(sysbus, &s->bonito_pciio); 662 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE); 663 664 /* add pci local io mapping */ 665 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "isa_mmio", 666 get_system_io(), 0, BONITO_DEV_SIZE); 667 sysbus_init_mmio(sysbus, &s->bonito_localio); 668 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE); 669 670 /* set the default value of north bridge pci config */ 671 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 672 pci_set_word(dev->config + PCI_STATUS, 0x0000); 673 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 674 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 675 676 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 677 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 678 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 679 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 680 681 qemu_register_reset(bonito_reset, s); 682 } 683 684 PCIBus *bonito_init(qemu_irq *pic) 685 { 686 DeviceState *dev; 687 BonitoState *pcihost; 688 PCIHostState *phb; 689 PCIBonitoState *s; 690 PCIDevice *d; 691 692 dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); 693 phb = PCI_HOST_BRIDGE(dev); 694 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 695 pcihost->pic = pic; 696 qdev_init_nofail(dev); 697 698 d = pci_create(phb->bus, PCI_DEVFN(0, 0), TYPE_PCI_BONITO); 699 s = PCI_BONITO(d); 700 s->pcihost = pcihost; 701 pcihost->pci_dev = s; 702 qdev_init_nofail(DEVICE(d)); 703 704 return phb->bus; 705 } 706 707 static void bonito_class_init(ObjectClass *klass, void *data) 708 { 709 DeviceClass *dc = DEVICE_CLASS(klass); 710 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 711 712 k->realize = bonito_realize; 713 k->vendor_id = 0xdf53; 714 k->device_id = 0x00d5; 715 k->revision = 0x01; 716 k->class_id = PCI_CLASS_BRIDGE_HOST; 717 dc->desc = "Host bridge"; 718 dc->vmsd = &vmstate_bonito; 719 /* 720 * PCI-facing part of the host bridge, not usable without the 721 * host-facing part, which can't be device_add'ed, yet. 722 */ 723 dc->user_creatable = false; 724 } 725 726 static const TypeInfo bonito_info = { 727 .name = TYPE_PCI_BONITO, 728 .parent = TYPE_PCI_DEVICE, 729 .instance_size = sizeof(PCIBonitoState), 730 .class_init = bonito_class_init, 731 .interfaces = (InterfaceInfo[]) { 732 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 733 { }, 734 }, 735 }; 736 737 static void bonito_pcihost_class_init(ObjectClass *klass, void *data) 738 { 739 DeviceClass *dc = DEVICE_CLASS(klass); 740 741 dc->realize = bonito_pcihost_realize; 742 } 743 744 static const TypeInfo bonito_pcihost_info = { 745 .name = TYPE_BONITO_PCI_HOST_BRIDGE, 746 .parent = TYPE_PCI_HOST_BRIDGE, 747 .instance_size = sizeof(BonitoState), 748 .class_init = bonito_pcihost_class_init, 749 }; 750 751 static void bonito_register_types(void) 752 { 753 type_register_static(&bonito_pcihost_info); 754 type_register_static(&bonito_info); 755 } 756 757 type_init(bonito_register_types) 758