1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * fuloong 2e mini pc has a bonito north bridge. 15 */ 16 17 /* 18 * what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 19 * 20 * devfn pci_slot<<3 + funno 21 * one pci bus can have 32 devices and each device can have 8 functions. 22 * 23 * In bonito north bridge, pci slot = IDSEL bit - 12. 24 * For example, PCI_IDSEL_VIA686B = 17, 25 * pci slot = 17-12=5 26 * 27 * so 28 * VT686B_FUN0's devfn = (5<<3)+0 29 * VT686B_FUN1's devfn = (5<<3)+1 30 * 31 * qemu also uses pci address for north bridge to access pci config register. 32 * bus_no [23:16] 33 * dev_no [15:11] 34 * fun_no [10:8] 35 * reg_no [7:2] 36 * 37 * so function bonito_sbridge_pciaddr for the translation from 38 * north bridge address to pci address. 39 */ 40 41 #include "qemu/osdep.h" 42 #include "qemu/units.h" 43 #include "qapi/error.h" 44 #include "qemu/error-report.h" 45 #include "hw/pci/pci.h" 46 #include "hw/irq.h" 47 #include "hw/mips/mips.h" 48 #include "hw/pci/pci_host.h" 49 #include "migration/vmstate.h" 50 #include "sysemu/reset.h" 51 #include "sysemu/runstate.h" 52 #include "exec/address-spaces.h" 53 #include "hw/misc/unimp.h" 54 #include "hw/registerfields.h" 55 #include "qom/object.h" 56 57 /* #define DEBUG_BONITO */ 58 59 #ifdef DEBUG_BONITO 60 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __func__, ##__VA_ARGS__) 61 #else 62 #define DPRINTF(fmt, ...) 63 #endif 64 65 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 66 #define BONITO_BOOT_BASE 0x1fc00000 67 #define BONITO_BOOT_SIZE 0x00100000 68 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE + BONITO_BOOT_SIZE - 1) 69 #define BONITO_FLASH_BASE 0x1c000000 70 #define BONITO_FLASH_SIZE 0x03000000 71 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE + BONITO_FLASH_SIZE - 1) 72 #define BONITO_SOCKET_BASE 0x1f800000 73 #define BONITO_SOCKET_SIZE 0x00400000 74 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE + BONITO_SOCKET_SIZE - 1) 75 #define BONITO_REG_BASE 0x1fe00000 76 #define BONITO_REG_SIZE 0x00040000 77 #define BONITO_REG_TOP (BONITO_REG_BASE + BONITO_REG_SIZE - 1) 78 #define BONITO_DEV_BASE 0x1ff00000 79 #define BONITO_DEV_SIZE 0x00100000 80 #define BONITO_DEV_TOP (BONITO_DEV_BASE + BONITO_DEV_SIZE - 1) 81 #define BONITO_PCILO_BASE 0x10000000 82 #define BONITO_PCILO_BASE_VA 0xb0000000 83 #define BONITO_PCILO_SIZE 0x0c000000 84 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE + BONITO_PCILO_SIZE - 1) 85 #define BONITO_PCILO0_BASE 0x10000000 86 #define BONITO_PCILO1_BASE 0x14000000 87 #define BONITO_PCILO2_BASE 0x18000000 88 #define BONITO_PCIHI_BASE 0x20000000 89 #define BONITO_PCIHI_SIZE 0x60000000 90 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE - 1) 91 #define BONITO_PCIIO_BASE 0x1fd00000 92 #define BONITO_PCIIO_BASE_VA 0xbfd00000 93 #define BONITO_PCIIO_SIZE 0x00010000 94 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE + BONITO_PCIIO_SIZE - 1) 95 #define BONITO_PCICFG_BASE 0x1fe80000 96 #define BONITO_PCICFG_SIZE 0x00080000 97 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE + BONITO_PCICFG_SIZE - 1) 98 99 100 #define BONITO_PCICONFIGBASE 0x00 101 #define BONITO_REGBASE 0x100 102 103 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE + BONITO_REG_BASE) 104 #define BONITO_PCICONFIG_SIZE (0x100) 105 106 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE + BONITO_REG_BASE) 107 #define BONITO_INTERNAL_REG_SIZE (0x70) 108 109 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 110 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 111 112 113 114 /* 1. Bonito h/w Configuration */ 115 /* Power on register */ 116 117 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 118 119 /* PCI configuration register */ 120 #define BONITO_BONGENCFG_OFFSET 0x4 121 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET >> 2) /*0x104 */ 122 REG32(BONGENCFG, 0x104) 123 FIELD(BONGENCFG, DEBUGMODE, 0, 1) 124 FIELD(BONGENCFG, SNOOP, 1, 1) 125 FIELD(BONGENCFG, CPUSELFRESET, 2, 1) 126 FIELD(BONGENCFG, BYTESWAP, 6, 1) 127 FIELD(BONGENCFG, UNCACHED, 7, 1) 128 FIELD(BONGENCFG, PREFETCH, 8, 1) 129 FIELD(BONGENCFG, WRITEBEHIND, 9, 1) 130 FIELD(BONGENCFG, PCIQUEUE, 12, 1) 131 132 /* 2. IO & IDE configuration */ 133 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 134 135 /* 3. IO & IDE configuration */ 136 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 137 138 /* 4. PCI address map control */ 139 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 140 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 141 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 142 143 /* 5. ICU & GPIO regs */ 144 /* GPIO Regs - r/w */ 145 #define BONITO_GPIODATA_OFFSET 0x1c 146 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 147 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 148 149 /* ICU Configuration Regs - r/w */ 150 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 151 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 152 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 153 154 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 155 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 156 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 157 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 158 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 159 160 /* PCI mail boxes */ 161 #define BONITO_PCIMAIL0_OFFSET 0x40 162 #define BONITO_PCIMAIL1_OFFSET 0x44 163 #define BONITO_PCIMAIL2_OFFSET 0x48 164 #define BONITO_PCIMAIL3_OFFSET 0x4c 165 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 166 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 167 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 168 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 169 170 /* 6. PCI cache */ 171 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 172 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 173 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 174 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 175 176 /* 7. other*/ 177 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 178 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 179 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 180 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 181 182 #define BONITO_REGS (0x70 >> 2) 183 184 /* PCI config for south bridge. type 0 */ 185 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 186 #define BONITO_PCICONF_IDSEL_OFFSET 11 187 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 188 #define BONITO_PCICONF_FUN_OFFSET 8 189 #define BONITO_PCICONF_REG_MASK 0xFC 190 #define BONITO_PCICONF_REG_OFFSET 0 191 192 193 /* idsel BIT = pci slot number +12 */ 194 #define PCI_SLOT_BASE 12 195 #define PCI_IDSEL_VIA686B_BIT (17) 196 #define PCI_IDSEL_VIA686B (1 << PCI_IDSEL_VIA686B_BIT) 197 198 #define PCI_ADDR(busno , devno , funno , regno) \ 199 ((((busno) << 16) & 0xff0000) + (((devno) << 11) & 0xf800) + \ 200 (((funno) << 8) & 0x700) + (regno)) 201 202 typedef struct BonitoState BonitoState; 203 204 struct PCIBonitoState { 205 PCIDevice dev; 206 207 BonitoState *pcihost; 208 uint32_t regs[BONITO_REGS]; 209 210 struct bonldma { 211 uint32_t ldmactrl; 212 uint32_t ldmastat; 213 uint32_t ldmaaddr; 214 uint32_t ldmago; 215 } bonldma; 216 217 /* Based at 1fe00300, bonito Copier */ 218 struct boncop { 219 uint32_t copctrl; 220 uint32_t copstat; 221 uint32_t coppaddr; 222 uint32_t copgo; 223 } boncop; 224 225 /* Bonito registers */ 226 MemoryRegion iomem; 227 MemoryRegion iomem_ldma; 228 MemoryRegion iomem_cop; 229 MemoryRegion bonito_pciio; 230 MemoryRegion bonito_localio; 231 232 }; 233 typedef struct PCIBonitoState PCIBonitoState; 234 235 struct BonitoState { 236 PCIHostState parent_obj; 237 qemu_irq *pic; 238 PCIBonitoState *pci_dev; 239 MemoryRegion pci_mem; 240 }; 241 242 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" 243 DECLARE_INSTANCE_CHECKER(BonitoState, BONITO_PCI_HOST_BRIDGE, 244 TYPE_BONITO_PCI_HOST_BRIDGE) 245 246 #define TYPE_PCI_BONITO "Bonito" 247 DECLARE_INSTANCE_CHECKER(PCIBonitoState, PCI_BONITO, 248 TYPE_PCI_BONITO) 249 250 static void bonito_writel(void *opaque, hwaddr addr, 251 uint64_t val, unsigned size) 252 { 253 PCIBonitoState *s = opaque; 254 uint32_t saddr; 255 int reset = 0; 256 257 saddr = addr >> 2; 258 259 DPRINTF("bonito_writel "TARGET_FMT_plx" val %lx saddr %x\n", 260 addr, val, saddr); 261 switch (saddr) { 262 case BONITO_BONPONCFG: 263 case BONITO_IODEVCFG: 264 case BONITO_SDCFG: 265 case BONITO_PCIMAP: 266 case BONITO_PCIMEMBASECFG: 267 case BONITO_PCIMAP_CFG: 268 case BONITO_GPIODATA: 269 case BONITO_GPIOIE: 270 case BONITO_INTEDGE: 271 case BONITO_INTSTEER: 272 case BONITO_INTPOL: 273 case BONITO_PCIMAIL0: 274 case BONITO_PCIMAIL1: 275 case BONITO_PCIMAIL2: 276 case BONITO_PCIMAIL3: 277 case BONITO_PCICACHECTRL: 278 case BONITO_PCICACHETAG: 279 case BONITO_PCIBADADDR: 280 case BONITO_PCIMSTAT: 281 case BONITO_TIMECFG: 282 case BONITO_CPUCFG: 283 case BONITO_DQCFG: 284 case BONITO_MEMSIZE: 285 s->regs[saddr] = val; 286 break; 287 case BONITO_BONGENCFG: 288 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 289 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 290 } 291 s->regs[saddr] = val; 292 if (reset) { 293 qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); 294 } 295 break; 296 case BONITO_INTENSET: 297 s->regs[BONITO_INTENSET] = val; 298 s->regs[BONITO_INTEN] |= val; 299 break; 300 case BONITO_INTENCLR: 301 s->regs[BONITO_INTENCLR] = val; 302 s->regs[BONITO_INTEN] &= ~val; 303 break; 304 case BONITO_INTEN: 305 case BONITO_INTISR: 306 DPRINTF("write to readonly bonito register %x\n", saddr); 307 break; 308 default: 309 DPRINTF("write to unknown bonito register %x\n", saddr); 310 break; 311 } 312 } 313 314 static uint64_t bonito_readl(void *opaque, hwaddr addr, 315 unsigned size) 316 { 317 PCIBonitoState *s = opaque; 318 uint32_t saddr; 319 320 saddr = addr >> 2; 321 322 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 323 switch (saddr) { 324 case BONITO_INTISR: 325 return s->regs[saddr]; 326 default: 327 return s->regs[saddr]; 328 } 329 } 330 331 static const MemoryRegionOps bonito_ops = { 332 .read = bonito_readl, 333 .write = bonito_writel, 334 .endianness = DEVICE_NATIVE_ENDIAN, 335 .valid = { 336 .min_access_size = 4, 337 .max_access_size = 4, 338 }, 339 }; 340 341 static void bonito_pciconf_writel(void *opaque, hwaddr addr, 342 uint64_t val, unsigned size) 343 { 344 PCIBonitoState *s = opaque; 345 PCIDevice *d = PCI_DEVICE(s); 346 347 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %lx\n", addr, val); 348 d->config_write(d, addr, val, 4); 349 } 350 351 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, 352 unsigned size) 353 { 354 355 PCIBonitoState *s = opaque; 356 PCIDevice *d = PCI_DEVICE(s); 357 358 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 359 return d->config_read(d, addr, 4); 360 } 361 362 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 363 364 static const MemoryRegionOps bonito_pciconf_ops = { 365 .read = bonito_pciconf_readl, 366 .write = bonito_pciconf_writel, 367 .endianness = DEVICE_NATIVE_ENDIAN, 368 .valid = { 369 .min_access_size = 4, 370 .max_access_size = 4, 371 }, 372 }; 373 374 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, 375 unsigned size) 376 { 377 uint32_t val; 378 PCIBonitoState *s = opaque; 379 380 if (addr >= sizeof(s->bonldma)) { 381 return 0; 382 } 383 384 val = ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)]; 385 386 return val; 387 } 388 389 static void bonito_ldma_writel(void *opaque, hwaddr addr, 390 uint64_t val, unsigned size) 391 { 392 PCIBonitoState *s = opaque; 393 394 if (addr >= sizeof(s->bonldma)) { 395 return; 396 } 397 398 ((uint32_t *)(&s->bonldma))[addr / sizeof(uint32_t)] = val & 0xffffffff; 399 } 400 401 static const MemoryRegionOps bonito_ldma_ops = { 402 .read = bonito_ldma_readl, 403 .write = bonito_ldma_writel, 404 .endianness = DEVICE_NATIVE_ENDIAN, 405 .valid = { 406 .min_access_size = 4, 407 .max_access_size = 4, 408 }, 409 }; 410 411 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, 412 unsigned size) 413 { 414 uint32_t val; 415 PCIBonitoState *s = opaque; 416 417 if (addr >= sizeof(s->boncop)) { 418 return 0; 419 } 420 421 val = ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)]; 422 423 return val; 424 } 425 426 static void bonito_cop_writel(void *opaque, hwaddr addr, 427 uint64_t val, unsigned size) 428 { 429 PCIBonitoState *s = opaque; 430 431 if (addr >= sizeof(s->boncop)) { 432 return; 433 } 434 435 ((uint32_t *)(&s->boncop))[addr / sizeof(uint32_t)] = val & 0xffffffff; 436 } 437 438 static const MemoryRegionOps bonito_cop_ops = { 439 .read = bonito_cop_readl, 440 .write = bonito_cop_writel, 441 .endianness = DEVICE_NATIVE_ENDIAN, 442 .valid = { 443 .min_access_size = 4, 444 .max_access_size = 4, 445 }, 446 }; 447 448 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) 449 { 450 PCIBonitoState *s = opaque; 451 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 452 uint32_t cfgaddr; 453 uint32_t idsel; 454 uint32_t devno; 455 uint32_t funno; 456 uint32_t regno; 457 uint32_t pciaddr; 458 459 /* support type0 pci config */ 460 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 461 return 0xffffffff; 462 } 463 464 cfgaddr = addr & 0xffff; 465 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 466 467 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> 468 BONITO_PCICONF_IDSEL_OFFSET; 469 devno = ctz32(idsel); 470 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 471 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 472 473 if (idsel == 0) { 474 error_report("error in bonito pci config address " TARGET_FMT_plx 475 ",pcimap_cfg=%x", addr, s->regs[BONITO_PCIMAP_CFG]); 476 exit(1); 477 } 478 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); 479 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 480 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); 481 482 return pciaddr; 483 } 484 485 static void bonito_spciconf_write(void *opaque, hwaddr addr, uint64_t val, 486 unsigned size) 487 { 488 PCIBonitoState *s = opaque; 489 PCIDevice *d = PCI_DEVICE(s); 490 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 491 uint32_t pciaddr; 492 uint16_t status; 493 494 DPRINTF("bonito_spciconf_write "TARGET_FMT_plx" size %d val %lx\n", 495 addr, size, val); 496 497 pciaddr = bonito_sbridge_pciaddr(s, addr); 498 499 if (pciaddr == 0xffffffff) { 500 return; 501 } 502 503 /* set the pci address in s->config_reg */ 504 phb->config_reg = (pciaddr) | (1u << 31); 505 pci_data_write(phb->bus, phb->config_reg, val, size); 506 507 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 508 status = pci_get_word(d->config + PCI_STATUS); 509 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 510 pci_set_word(d->config + PCI_STATUS, status); 511 } 512 513 static uint64_t bonito_spciconf_read(void *opaque, hwaddr addr, unsigned size) 514 { 515 PCIBonitoState *s = opaque; 516 PCIDevice *d = PCI_DEVICE(s); 517 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 518 uint32_t pciaddr; 519 uint16_t status; 520 521 DPRINTF("bonito_spciconf_read "TARGET_FMT_plx" size %d\n", addr, size); 522 523 pciaddr = bonito_sbridge_pciaddr(s, addr); 524 525 if (pciaddr == 0xffffffff) { 526 return MAKE_64BIT_MASK(0, size * 8); 527 } 528 529 /* set the pci address in s->config_reg */ 530 phb->config_reg = (pciaddr) | (1u << 31); 531 532 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 533 status = pci_get_word(d->config + PCI_STATUS); 534 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 535 pci_set_word(d->config + PCI_STATUS, status); 536 537 return pci_data_read(phb->bus, phb->config_reg, size); 538 } 539 540 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 541 static const MemoryRegionOps bonito_spciconf_ops = { 542 .read = bonito_spciconf_read, 543 .write = bonito_spciconf_write, 544 .valid.min_access_size = 1, 545 .valid.max_access_size = 4, 546 .impl.min_access_size = 1, 547 .impl.max_access_size = 4, 548 .endianness = DEVICE_NATIVE_ENDIAN, 549 }; 550 551 #define BONITO_IRQ_BASE 32 552 553 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 554 { 555 BonitoState *s = opaque; 556 qemu_irq *pic = s->pic; 557 PCIBonitoState *bonito_state = s->pci_dev; 558 int internal_irq = irq_num - BONITO_IRQ_BASE; 559 560 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { 561 qemu_irq_pulse(*pic); 562 } else { /* level triggered */ 563 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { 564 qemu_irq_raise(*pic); 565 } else { 566 qemu_irq_lower(*pic); 567 } 568 } 569 } 570 571 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 572 static int pci_bonito_map_irq(PCIDevice *pci_dev, int irq_num) 573 { 574 int slot; 575 576 slot = (pci_dev->devfn >> 3); 577 578 switch (slot) { 579 case 5: /* FULOONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 580 return irq_num % 4 + BONITO_IRQ_BASE; 581 case 6: /* FULOONG2E_ATI_SLOT, VGA */ 582 return 4 + BONITO_IRQ_BASE; 583 case 7: /* FULOONG2E_RTL_SLOT, RTL8139 */ 584 return 5 + BONITO_IRQ_BASE; 585 case 8 ... 12: /* PCI slot 1 to 4 */ 586 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 587 default: /* Unknown device, don't do any translation */ 588 return irq_num; 589 } 590 } 591 592 static void bonito_reset(void *opaque) 593 { 594 PCIBonitoState *s = opaque; 595 uint32_t val = 0; 596 597 /* set the default value of north bridge registers */ 598 599 s->regs[BONITO_BONPONCFG] = 0xc40; 600 val = FIELD_DP32(val, BONGENCFG, PCIQUEUE, 1); 601 val = FIELD_DP32(val, BONGENCFG, WRITEBEHIND, 1); 602 val = FIELD_DP32(val, BONGENCFG, PREFETCH, 1); 603 val = FIELD_DP32(val, BONGENCFG, UNCACHED, 1); 604 val = FIELD_DP32(val, BONGENCFG, CPUSELFRESET, 1); 605 s->regs[BONITO_BONGENCFG] = val; 606 607 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 608 s->regs[BONITO_SDCFG] = 0x255e0091; 609 610 s->regs[BONITO_GPIODATA] = 0x1ff; 611 s->regs[BONITO_GPIOIE] = 0x1ff; 612 s->regs[BONITO_DQCFG] = 0x8; 613 s->regs[BONITO_MEMSIZE] = 0x10000000; 614 s->regs[BONITO_PCIMAP] = 0x6140; 615 } 616 617 static const VMStateDescription vmstate_bonito = { 618 .name = "Bonito", 619 .version_id = 1, 620 .minimum_version_id = 1, 621 .fields = (VMStateField[]) { 622 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 623 VMSTATE_END_OF_LIST() 624 } 625 }; 626 627 static void bonito_pcihost_realize(DeviceState *dev, Error **errp) 628 { 629 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 630 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(dev); 631 MemoryRegion *pcimem_lo_alias = g_new(MemoryRegion, 3); 632 633 memory_region_init(&bs->pci_mem, OBJECT(dev), "pci.mem", BONITO_PCIHI_SIZE); 634 phb->bus = pci_register_root_bus(dev, "pci", 635 pci_bonito_set_irq, pci_bonito_map_irq, 636 dev, &bs->pci_mem, get_system_io(), 637 0x28, 32, TYPE_PCI_BUS); 638 639 for (size_t i = 0; i < 3; i++) { 640 char *name = g_strdup_printf("pci.lomem%zu", i); 641 642 memory_region_init_alias(&pcimem_lo_alias[i], NULL, name, 643 &bs->pci_mem, i * 64 * MiB, 64 * MiB); 644 memory_region_add_subregion(get_system_memory(), 645 BONITO_PCILO_BASE + i * 64 * MiB, 646 &pcimem_lo_alias[i]); 647 g_free(name); 648 } 649 650 create_unimplemented_device("pci.io", BONITO_PCIIO_BASE, 1 * MiB); 651 } 652 653 static void bonito_realize(PCIDevice *dev, Error **errp) 654 { 655 PCIBonitoState *s = PCI_BONITO(dev); 656 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); 657 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 658 BonitoState *bs = BONITO_PCI_HOST_BRIDGE(s->pcihost); 659 MemoryRegion *pcimem_alias = g_new(MemoryRegion, 1); 660 661 /* 662 * Bonito North Bridge, built on FPGA, 663 * VENDOR_ID/DEVICE_ID are "undefined" 664 */ 665 pci_config_set_prog_interface(dev->config, 0x00); 666 667 /* set the north bridge register mapping */ 668 memory_region_init_io(&s->iomem, OBJECT(s), &bonito_ops, s, 669 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 670 sysbus_init_mmio(sysbus, &s->iomem); 671 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 672 673 /* set the north bridge pci configure mapping */ 674 memory_region_init_io(&phb->conf_mem, OBJECT(s), &bonito_pciconf_ops, s, 675 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 676 sysbus_init_mmio(sysbus, &phb->conf_mem); 677 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 678 679 /* set the south bridge pci configure mapping */ 680 memory_region_init_io(&phb->data_mem, OBJECT(s), &bonito_spciconf_ops, s, 681 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 682 sysbus_init_mmio(sysbus, &phb->data_mem); 683 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 684 685 create_unimplemented_device("bonito", BONITO_REG_BASE, BONITO_REG_SIZE); 686 687 memory_region_init_io(&s->iomem_ldma, OBJECT(s), &bonito_ldma_ops, s, 688 "ldma", 0x100); 689 sysbus_init_mmio(sysbus, &s->iomem_ldma); 690 sysbus_mmio_map(sysbus, 3, 0x1fe00200); 691 692 /* PCI copier */ 693 memory_region_init_io(&s->iomem_cop, OBJECT(s), &bonito_cop_ops, s, 694 "cop", 0x100); 695 sysbus_init_mmio(sysbus, &s->iomem_cop); 696 sysbus_mmio_map(sysbus, 4, 0x1fe00300); 697 698 create_unimplemented_device("ROMCS", BONITO_FLASH_BASE, 60 * MiB); 699 700 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 701 memory_region_init_alias(&s->bonito_pciio, OBJECT(s), "isa_mmio", 702 get_system_io(), 0, BONITO_PCIIO_SIZE); 703 sysbus_init_mmio(sysbus, &s->bonito_pciio); 704 sysbus_mmio_map(sysbus, 5, BONITO_PCIIO_BASE); 705 706 /* add pci local io mapping */ 707 708 memory_region_init_alias(&s->bonito_localio, OBJECT(s), "IOCS[0]", 709 get_system_io(), 0, 256 * KiB); 710 sysbus_init_mmio(sysbus, &s->bonito_localio); 711 sysbus_mmio_map(sysbus, 6, BONITO_DEV_BASE); 712 create_unimplemented_device("IOCS[1]", BONITO_DEV_BASE + 1 * 256 * KiB, 713 256 * KiB); 714 create_unimplemented_device("IOCS[2]", BONITO_DEV_BASE + 2 * 256 * KiB, 715 256 * KiB); 716 create_unimplemented_device("IOCS[3]", BONITO_DEV_BASE + 3 * 256 * KiB, 717 256 * KiB); 718 719 memory_region_init_alias(pcimem_alias, NULL, "pci.mem.alias", 720 &bs->pci_mem, 0, BONITO_PCIHI_SIZE); 721 memory_region_add_subregion(get_system_memory(), 722 BONITO_PCIHI_BASE, pcimem_alias); 723 create_unimplemented_device("PCI_2", 724 (hwaddr)BONITO_PCIHI_BASE + BONITO_PCIHI_SIZE, 725 2 * GiB); 726 727 /* set the default value of north bridge pci config */ 728 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 729 pci_set_word(dev->config + PCI_STATUS, 0x0000); 730 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 731 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 732 733 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 734 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 735 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 736 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 737 738 qemu_register_reset(bonito_reset, s); 739 } 740 741 PCIBus *bonito_init(qemu_irq *pic) 742 { 743 DeviceState *dev; 744 BonitoState *pcihost; 745 PCIHostState *phb; 746 PCIBonitoState *s; 747 PCIDevice *d; 748 749 dev = qdev_new(TYPE_BONITO_PCI_HOST_BRIDGE); 750 phb = PCI_HOST_BRIDGE(dev); 751 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 752 pcihost->pic = pic; 753 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 754 755 d = pci_new(PCI_DEVFN(0, 0), TYPE_PCI_BONITO); 756 s = PCI_BONITO(d); 757 s->pcihost = pcihost; 758 pcihost->pci_dev = s; 759 pci_realize_and_unref(d, phb->bus, &error_fatal); 760 761 return phb->bus; 762 } 763 764 static void bonito_class_init(ObjectClass *klass, void *data) 765 { 766 DeviceClass *dc = DEVICE_CLASS(klass); 767 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 768 769 k->realize = bonito_realize; 770 k->vendor_id = 0xdf53; 771 k->device_id = 0x00d5; 772 k->revision = 0x01; 773 k->class_id = PCI_CLASS_BRIDGE_HOST; 774 dc->desc = "Host bridge"; 775 dc->vmsd = &vmstate_bonito; 776 /* 777 * PCI-facing part of the host bridge, not usable without the 778 * host-facing part, which can't be device_add'ed, yet. 779 */ 780 dc->user_creatable = false; 781 } 782 783 static const TypeInfo bonito_info = { 784 .name = TYPE_PCI_BONITO, 785 .parent = TYPE_PCI_DEVICE, 786 .instance_size = sizeof(PCIBonitoState), 787 .class_init = bonito_class_init, 788 .interfaces = (InterfaceInfo[]) { 789 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 790 { }, 791 }, 792 }; 793 794 static void bonito_pcihost_class_init(ObjectClass *klass, void *data) 795 { 796 DeviceClass *dc = DEVICE_CLASS(klass); 797 798 dc->realize = bonito_pcihost_realize; 799 } 800 801 static const TypeInfo bonito_pcihost_info = { 802 .name = TYPE_BONITO_PCI_HOST_BRIDGE, 803 .parent = TYPE_PCI_HOST_BRIDGE, 804 .instance_size = sizeof(BonitoState), 805 .class_init = bonito_pcihost_class_init, 806 }; 807 808 static void bonito_register_types(void) 809 { 810 type_register_static(&bonito_pcihost_info); 811 type_register_static(&bonito_info); 812 } 813 814 type_init(bonito_register_types) 815