1 /* 2 * bonito north bridge support 3 * 4 * Copyright (c) 2008 yajin (yajin@vm-kernel.org) 5 * Copyright (c) 2010 Huacai Chen (zltjiangshi@gmail.com) 6 * 7 * This code is licensed under the GNU GPL v2. 8 * 9 * Contributions after 2012-01-13 are licensed under the terms of the 10 * GNU GPL, version 2 or (at your option) any later version. 11 */ 12 13 /* 14 * fulong 2e mini pc has a bonito north bridge. 15 */ 16 17 /* what is the meaning of devfn in qemu and IDSEL in bonito northbridge? 18 * 19 * devfn pci_slot<<3 + funno 20 * one pci bus can have 32 devices and each device can have 8 functions. 21 * 22 * In bonito north bridge, pci slot = IDSEL bit - 12. 23 * For example, PCI_IDSEL_VIA686B = 17, 24 * pci slot = 17-12=5 25 * 26 * so 27 * VT686B_FUN0's devfn = (5<<3)+0 28 * VT686B_FUN1's devfn = (5<<3)+1 29 * 30 * qemu also uses pci address for north bridge to access pci config register. 31 * bus_no [23:16] 32 * dev_no [15:11] 33 * fun_no [10:8] 34 * reg_no [7:2] 35 * 36 * so function bonito_sbridge_pciaddr for the translation from 37 * north bridge address to pci address. 38 */ 39 40 #include <assert.h> 41 42 #include "hw/hw.h" 43 #include "hw/pci/pci.h" 44 #include "hw/i386/pc.h" 45 #include "hw/mips/mips.h" 46 #include "hw/pci/pci_host.h" 47 #include "sysemu/sysemu.h" 48 #include "exec/address-spaces.h" 49 50 //#define DEBUG_BONITO 51 52 #ifdef DEBUG_BONITO 53 #define DPRINTF(fmt, ...) fprintf(stderr, "%s: " fmt, __FUNCTION__, ##__VA_ARGS__) 54 #else 55 #define DPRINTF(fmt, ...) 56 #endif 57 58 /* from linux soure code. include/asm-mips/mips-boards/bonito64.h*/ 59 #define BONITO_BOOT_BASE 0x1fc00000 60 #define BONITO_BOOT_SIZE 0x00100000 61 #define BONITO_BOOT_TOP (BONITO_BOOT_BASE+BONITO_BOOT_SIZE-1) 62 #define BONITO_FLASH_BASE 0x1c000000 63 #define BONITO_FLASH_SIZE 0x03000000 64 #define BONITO_FLASH_TOP (BONITO_FLASH_BASE+BONITO_FLASH_SIZE-1) 65 #define BONITO_SOCKET_BASE 0x1f800000 66 #define BONITO_SOCKET_SIZE 0x00400000 67 #define BONITO_SOCKET_TOP (BONITO_SOCKET_BASE+BONITO_SOCKET_SIZE-1) 68 #define BONITO_REG_BASE 0x1fe00000 69 #define BONITO_REG_SIZE 0x00040000 70 #define BONITO_REG_TOP (BONITO_REG_BASE+BONITO_REG_SIZE-1) 71 #define BONITO_DEV_BASE 0x1ff00000 72 #define BONITO_DEV_SIZE 0x00100000 73 #define BONITO_DEV_TOP (BONITO_DEV_BASE+BONITO_DEV_SIZE-1) 74 #define BONITO_PCILO_BASE 0x10000000 75 #define BONITO_PCILO_BASE_VA 0xb0000000 76 #define BONITO_PCILO_SIZE 0x0c000000 77 #define BONITO_PCILO_TOP (BONITO_PCILO_BASE+BONITO_PCILO_SIZE-1) 78 #define BONITO_PCILO0_BASE 0x10000000 79 #define BONITO_PCILO1_BASE 0x14000000 80 #define BONITO_PCILO2_BASE 0x18000000 81 #define BONITO_PCIHI_BASE 0x20000000 82 #define BONITO_PCIHI_SIZE 0x20000000 83 #define BONITO_PCIHI_TOP (BONITO_PCIHI_BASE+BONITO_PCIHI_SIZE-1) 84 #define BONITO_PCIIO_BASE 0x1fd00000 85 #define BONITO_PCIIO_BASE_VA 0xbfd00000 86 #define BONITO_PCIIO_SIZE 0x00010000 87 #define BONITO_PCIIO_TOP (BONITO_PCIIO_BASE+BONITO_PCIIO_SIZE-1) 88 #define BONITO_PCICFG_BASE 0x1fe80000 89 #define BONITO_PCICFG_SIZE 0x00080000 90 #define BONITO_PCICFG_TOP (BONITO_PCICFG_BASE+BONITO_PCICFG_SIZE-1) 91 92 93 #define BONITO_PCICONFIGBASE 0x00 94 #define BONITO_REGBASE 0x100 95 96 #define BONITO_PCICONFIG_BASE (BONITO_PCICONFIGBASE+BONITO_REG_BASE) 97 #define BONITO_PCICONFIG_SIZE (0x100) 98 99 #define BONITO_INTERNAL_REG_BASE (BONITO_REGBASE+BONITO_REG_BASE) 100 #define BONITO_INTERNAL_REG_SIZE (0x70) 101 102 #define BONITO_SPCICONFIG_BASE (BONITO_PCICFG_BASE) 103 #define BONITO_SPCICONFIG_SIZE (BONITO_PCICFG_SIZE) 104 105 106 107 /* 1. Bonito h/w Configuration */ 108 /* Power on register */ 109 110 #define BONITO_BONPONCFG (0x00 >> 2) /* 0x100 */ 111 #define BONITO_BONGENCFG_OFFSET 0x4 112 #define BONITO_BONGENCFG (BONITO_BONGENCFG_OFFSET>>2) /*0x104 */ 113 114 /* 2. IO & IDE configuration */ 115 #define BONITO_IODEVCFG (0x08 >> 2) /* 0x108 */ 116 117 /* 3. IO & IDE configuration */ 118 #define BONITO_SDCFG (0x0c >> 2) /* 0x10c */ 119 120 /* 4. PCI address map control */ 121 #define BONITO_PCIMAP (0x10 >> 2) /* 0x110 */ 122 #define BONITO_PCIMEMBASECFG (0x14 >> 2) /* 0x114 */ 123 #define BONITO_PCIMAP_CFG (0x18 >> 2) /* 0x118 */ 124 125 /* 5. ICU & GPIO regs */ 126 /* GPIO Regs - r/w */ 127 #define BONITO_GPIODATA_OFFSET 0x1c 128 #define BONITO_GPIODATA (BONITO_GPIODATA_OFFSET >> 2) /* 0x11c */ 129 #define BONITO_GPIOIE (0x20 >> 2) /* 0x120 */ 130 131 /* ICU Configuration Regs - r/w */ 132 #define BONITO_INTEDGE (0x24 >> 2) /* 0x124 */ 133 #define BONITO_INTSTEER (0x28 >> 2) /* 0x128 */ 134 #define BONITO_INTPOL (0x2c >> 2) /* 0x12c */ 135 136 /* ICU Enable Regs - IntEn & IntISR are r/o. */ 137 #define BONITO_INTENSET (0x30 >> 2) /* 0x130 */ 138 #define BONITO_INTENCLR (0x34 >> 2) /* 0x134 */ 139 #define BONITO_INTEN (0x38 >> 2) /* 0x138 */ 140 #define BONITO_INTISR (0x3c >> 2) /* 0x13c */ 141 142 /* PCI mail boxes */ 143 #define BONITO_PCIMAIL0_OFFSET 0x40 144 #define BONITO_PCIMAIL1_OFFSET 0x44 145 #define BONITO_PCIMAIL2_OFFSET 0x48 146 #define BONITO_PCIMAIL3_OFFSET 0x4c 147 #define BONITO_PCIMAIL0 (0x40 >> 2) /* 0x140 */ 148 #define BONITO_PCIMAIL1 (0x44 >> 2) /* 0x144 */ 149 #define BONITO_PCIMAIL2 (0x48 >> 2) /* 0x148 */ 150 #define BONITO_PCIMAIL3 (0x4c >> 2) /* 0x14c */ 151 152 /* 6. PCI cache */ 153 #define BONITO_PCICACHECTRL (0x50 >> 2) /* 0x150 */ 154 #define BONITO_PCICACHETAG (0x54 >> 2) /* 0x154 */ 155 #define BONITO_PCIBADADDR (0x58 >> 2) /* 0x158 */ 156 #define BONITO_PCIMSTAT (0x5c >> 2) /* 0x15c */ 157 158 /* 7. other*/ 159 #define BONITO_TIMECFG (0x60 >> 2) /* 0x160 */ 160 #define BONITO_CPUCFG (0x64 >> 2) /* 0x164 */ 161 #define BONITO_DQCFG (0x68 >> 2) /* 0x168 */ 162 #define BONITO_MEMSIZE (0x6C >> 2) /* 0x16c */ 163 164 #define BONITO_REGS (0x70 >> 2) 165 166 /* PCI config for south bridge. type 0 */ 167 #define BONITO_PCICONF_IDSEL_MASK 0xfffff800 /* [31:11] */ 168 #define BONITO_PCICONF_IDSEL_OFFSET 11 169 #define BONITO_PCICONF_FUN_MASK 0x700 /* [10:8] */ 170 #define BONITO_PCICONF_FUN_OFFSET 8 171 #define BONITO_PCICONF_REG_MASK 0xFC 172 #define BONITO_PCICONF_REG_OFFSET 0 173 174 175 /* idsel BIT = pci slot number +12 */ 176 #define PCI_SLOT_BASE 12 177 #define PCI_IDSEL_VIA686B_BIT (17) 178 #define PCI_IDSEL_VIA686B (1<<PCI_IDSEL_VIA686B_BIT) 179 180 #define PCI_ADDR(busno,devno,funno,regno) \ 181 ((((busno)<<16)&0xff0000) + (((devno)<<11)&0xf800) + (((funno)<<8)&0x700) + (regno)) 182 183 #define TYPE_BONITO_PCI_HOST_BRIDGE "Bonito-pcihost" 184 185 typedef struct BonitoState BonitoState; 186 187 typedef struct PCIBonitoState 188 { 189 PCIDevice dev; 190 191 BonitoState *pcihost; 192 uint32_t regs[BONITO_REGS]; 193 194 struct bonldma { 195 uint32_t ldmactrl; 196 uint32_t ldmastat; 197 uint32_t ldmaaddr; 198 uint32_t ldmago; 199 } bonldma; 200 201 /* Based at 1fe00300, bonito Copier */ 202 struct boncop { 203 uint32_t copctrl; 204 uint32_t copstat; 205 uint32_t coppaddr; 206 uint32_t copgo; 207 } boncop; 208 209 /* Bonito registers */ 210 MemoryRegion iomem; 211 MemoryRegion iomem_ldma; 212 MemoryRegion iomem_cop; 213 214 hwaddr bonito_pciio_start; 215 hwaddr bonito_pciio_length; 216 int bonito_pciio_handle; 217 218 hwaddr bonito_localio_start; 219 hwaddr bonito_localio_length; 220 int bonito_localio_handle; 221 222 } PCIBonitoState; 223 224 #define BONITO_PCI_HOST_BRIDGE(obj) \ 225 OBJECT_CHECK(BonitoState, (obj), TYPE_BONITO_PCI_HOST_BRIDGE) 226 227 struct BonitoState { 228 PCIHostState parent_obj; 229 230 qemu_irq *pic; 231 232 PCIBonitoState *pci_dev; 233 }; 234 235 static void bonito_writel(void *opaque, hwaddr addr, 236 uint64_t val, unsigned size) 237 { 238 PCIBonitoState *s = opaque; 239 uint32_t saddr; 240 int reset = 0; 241 242 saddr = (addr - BONITO_REGBASE) >> 2; 243 244 DPRINTF("bonito_writel "TARGET_FMT_plx" val %x saddr %x\n", addr, val, saddr); 245 switch (saddr) { 246 case BONITO_BONPONCFG: 247 case BONITO_IODEVCFG: 248 case BONITO_SDCFG: 249 case BONITO_PCIMAP: 250 case BONITO_PCIMEMBASECFG: 251 case BONITO_PCIMAP_CFG: 252 case BONITO_GPIODATA: 253 case BONITO_GPIOIE: 254 case BONITO_INTEDGE: 255 case BONITO_INTSTEER: 256 case BONITO_INTPOL: 257 case BONITO_PCIMAIL0: 258 case BONITO_PCIMAIL1: 259 case BONITO_PCIMAIL2: 260 case BONITO_PCIMAIL3: 261 case BONITO_PCICACHECTRL: 262 case BONITO_PCICACHETAG: 263 case BONITO_PCIBADADDR: 264 case BONITO_PCIMSTAT: 265 case BONITO_TIMECFG: 266 case BONITO_CPUCFG: 267 case BONITO_DQCFG: 268 case BONITO_MEMSIZE: 269 s->regs[saddr] = val; 270 break; 271 case BONITO_BONGENCFG: 272 if (!(s->regs[saddr] & 0x04) && (val & 0x04)) { 273 reset = 1; /* bit 2 jump from 0 to 1 cause reset */ 274 } 275 s->regs[saddr] = val; 276 if (reset) { 277 qemu_system_reset_request(); 278 } 279 break; 280 case BONITO_INTENSET: 281 s->regs[BONITO_INTENSET] = val; 282 s->regs[BONITO_INTEN] |= val; 283 break; 284 case BONITO_INTENCLR: 285 s->regs[BONITO_INTENCLR] = val; 286 s->regs[BONITO_INTEN] &= ~val; 287 break; 288 case BONITO_INTEN: 289 case BONITO_INTISR: 290 DPRINTF("write to readonly bonito register %x\n", saddr); 291 break; 292 default: 293 DPRINTF("write to unknown bonito register %x\n", saddr); 294 break; 295 } 296 } 297 298 static uint64_t bonito_readl(void *opaque, hwaddr addr, 299 unsigned size) 300 { 301 PCIBonitoState *s = opaque; 302 uint32_t saddr; 303 304 saddr = (addr - BONITO_REGBASE) >> 2; 305 306 DPRINTF("bonito_readl "TARGET_FMT_plx"\n", addr); 307 switch (saddr) { 308 case BONITO_INTISR: 309 return s->regs[saddr]; 310 default: 311 return s->regs[saddr]; 312 } 313 } 314 315 static const MemoryRegionOps bonito_ops = { 316 .read = bonito_readl, 317 .write = bonito_writel, 318 .endianness = DEVICE_NATIVE_ENDIAN, 319 .valid = { 320 .min_access_size = 4, 321 .max_access_size = 4, 322 }, 323 }; 324 325 static void bonito_pciconf_writel(void *opaque, hwaddr addr, 326 uint64_t val, unsigned size) 327 { 328 PCIBonitoState *s = opaque; 329 PCIDevice *d = PCI_DEVICE(s); 330 331 DPRINTF("bonito_pciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 332 d->config_write(d, addr, val, 4); 333 } 334 335 static uint64_t bonito_pciconf_readl(void *opaque, hwaddr addr, 336 unsigned size) 337 { 338 339 PCIBonitoState *s = opaque; 340 PCIDevice *d = PCI_DEVICE(s); 341 342 DPRINTF("bonito_pciconf_readl "TARGET_FMT_plx"\n", addr); 343 return d->config_read(d, addr, 4); 344 } 345 346 /* north bridge PCI configure space. 0x1fe0 0000 - 0x1fe0 00ff */ 347 348 static const MemoryRegionOps bonito_pciconf_ops = { 349 .read = bonito_pciconf_readl, 350 .write = bonito_pciconf_writel, 351 .endianness = DEVICE_NATIVE_ENDIAN, 352 .valid = { 353 .min_access_size = 4, 354 .max_access_size = 4, 355 }, 356 }; 357 358 static uint64_t bonito_ldma_readl(void *opaque, hwaddr addr, 359 unsigned size) 360 { 361 uint32_t val; 362 PCIBonitoState *s = opaque; 363 364 val = ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)]; 365 366 return val; 367 } 368 369 static void bonito_ldma_writel(void *opaque, hwaddr addr, 370 uint64_t val, unsigned size) 371 { 372 PCIBonitoState *s = opaque; 373 374 ((uint32_t *)(&s->bonldma))[addr/sizeof(uint32_t)] = val & 0xffffffff; 375 } 376 377 static const MemoryRegionOps bonito_ldma_ops = { 378 .read = bonito_ldma_readl, 379 .write = bonito_ldma_writel, 380 .endianness = DEVICE_NATIVE_ENDIAN, 381 .valid = { 382 .min_access_size = 4, 383 .max_access_size = 4, 384 }, 385 }; 386 387 static uint64_t bonito_cop_readl(void *opaque, hwaddr addr, 388 unsigned size) 389 { 390 uint32_t val; 391 PCIBonitoState *s = opaque; 392 393 val = ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)]; 394 395 return val; 396 } 397 398 static void bonito_cop_writel(void *opaque, hwaddr addr, 399 uint64_t val, unsigned size) 400 { 401 PCIBonitoState *s = opaque; 402 403 ((uint32_t *)(&s->boncop))[addr/sizeof(uint32_t)] = val & 0xffffffff; 404 } 405 406 static const MemoryRegionOps bonito_cop_ops = { 407 .read = bonito_cop_readl, 408 .write = bonito_cop_writel, 409 .endianness = DEVICE_NATIVE_ENDIAN, 410 .valid = { 411 .min_access_size = 4, 412 .max_access_size = 4, 413 }, 414 }; 415 416 static uint32_t bonito_sbridge_pciaddr(void *opaque, hwaddr addr) 417 { 418 PCIBonitoState *s = opaque; 419 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 420 uint32_t cfgaddr; 421 uint32_t idsel; 422 uint32_t devno; 423 uint32_t funno; 424 uint32_t regno; 425 uint32_t pciaddr; 426 427 /* support type0 pci config */ 428 if ((s->regs[BONITO_PCIMAP_CFG] & 0x10000) != 0x0) { 429 return 0xffffffff; 430 } 431 432 cfgaddr = addr & 0xffff; 433 cfgaddr |= (s->regs[BONITO_PCIMAP_CFG] & 0xffff) << 16; 434 435 idsel = (cfgaddr & BONITO_PCICONF_IDSEL_MASK) >> BONITO_PCICONF_IDSEL_OFFSET; 436 devno = ffs(idsel) - 1; 437 funno = (cfgaddr & BONITO_PCICONF_FUN_MASK) >> BONITO_PCICONF_FUN_OFFSET; 438 regno = (cfgaddr & BONITO_PCICONF_REG_MASK) >> BONITO_PCICONF_REG_OFFSET; 439 440 if (idsel == 0) { 441 fprintf(stderr, "error in bonito pci config address " TARGET_FMT_plx 442 ",pcimap_cfg=%x\n", addr, s->regs[BONITO_PCIMAP_CFG]); 443 exit(1); 444 } 445 pciaddr = PCI_ADDR(pci_bus_num(phb->bus), devno, funno, regno); 446 DPRINTF("cfgaddr %x pciaddr %x busno %x devno %d funno %d regno %d\n", 447 cfgaddr, pciaddr, pci_bus_num(phb->bus), devno, funno, regno); 448 449 return pciaddr; 450 } 451 452 static void bonito_spciconf_writeb(void *opaque, hwaddr addr, 453 uint32_t val) 454 { 455 PCIBonitoState *s = opaque; 456 PCIDevice *d = PCI_DEVICE(s); 457 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 458 uint32_t pciaddr; 459 uint16_t status; 460 461 DPRINTF("bonito_spciconf_writeb "TARGET_FMT_plx" val %x\n", addr, val); 462 pciaddr = bonito_sbridge_pciaddr(s, addr); 463 464 if (pciaddr == 0xffffffff) { 465 return; 466 } 467 468 /* set the pci address in s->config_reg */ 469 phb->config_reg = (pciaddr) | (1u << 31); 470 pci_data_write(phb->bus, phb->config_reg, val & 0xff, 1); 471 472 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 473 status = pci_get_word(d->config + PCI_STATUS); 474 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 475 pci_set_word(d->config + PCI_STATUS, status); 476 } 477 478 static void bonito_spciconf_writew(void *opaque, hwaddr addr, 479 uint32_t val) 480 { 481 PCIBonitoState *s = opaque; 482 PCIDevice *d = PCI_DEVICE(s); 483 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 484 uint32_t pciaddr; 485 uint16_t status; 486 487 DPRINTF("bonito_spciconf_writew "TARGET_FMT_plx" val %x\n", addr, val); 488 assert((addr & 0x1) == 0); 489 490 pciaddr = bonito_sbridge_pciaddr(s, addr); 491 492 if (pciaddr == 0xffffffff) { 493 return; 494 } 495 496 /* set the pci address in s->config_reg */ 497 phb->config_reg = (pciaddr) | (1u << 31); 498 pci_data_write(phb->bus, phb->config_reg, val, 2); 499 500 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 501 status = pci_get_word(d->config + PCI_STATUS); 502 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 503 pci_set_word(d->config + PCI_STATUS, status); 504 } 505 506 static void bonito_spciconf_writel(void *opaque, hwaddr addr, 507 uint32_t val) 508 { 509 PCIBonitoState *s = opaque; 510 PCIDevice *d = PCI_DEVICE(s); 511 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 512 uint32_t pciaddr; 513 uint16_t status; 514 515 DPRINTF("bonito_spciconf_writel "TARGET_FMT_plx" val %x\n", addr, val); 516 assert((addr & 0x3) == 0); 517 518 pciaddr = bonito_sbridge_pciaddr(s, addr); 519 520 if (pciaddr == 0xffffffff) { 521 return; 522 } 523 524 /* set the pci address in s->config_reg */ 525 phb->config_reg = (pciaddr) | (1u << 31); 526 pci_data_write(phb->bus, phb->config_reg, val, 4); 527 528 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 529 status = pci_get_word(d->config + PCI_STATUS); 530 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 531 pci_set_word(d->config + PCI_STATUS, status); 532 } 533 534 static uint32_t bonito_spciconf_readb(void *opaque, hwaddr addr) 535 { 536 PCIBonitoState *s = opaque; 537 PCIDevice *d = PCI_DEVICE(s); 538 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 539 uint32_t pciaddr; 540 uint16_t status; 541 542 DPRINTF("bonito_spciconf_readb "TARGET_FMT_plx"\n", addr); 543 pciaddr = bonito_sbridge_pciaddr(s, addr); 544 545 if (pciaddr == 0xffffffff) { 546 return 0xff; 547 } 548 549 /* set the pci address in s->config_reg */ 550 phb->config_reg = (pciaddr) | (1u << 31); 551 552 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 553 status = pci_get_word(d->config + PCI_STATUS); 554 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 555 pci_set_word(d->config + PCI_STATUS, status); 556 557 return pci_data_read(phb->bus, phb->config_reg, 1); 558 } 559 560 static uint32_t bonito_spciconf_readw(void *opaque, hwaddr addr) 561 { 562 PCIBonitoState *s = opaque; 563 PCIDevice *d = PCI_DEVICE(s); 564 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 565 uint32_t pciaddr; 566 uint16_t status; 567 568 DPRINTF("bonito_spciconf_readw "TARGET_FMT_plx"\n", addr); 569 assert((addr & 0x1) == 0); 570 571 pciaddr = bonito_sbridge_pciaddr(s, addr); 572 573 if (pciaddr == 0xffffffff) { 574 return 0xffff; 575 } 576 577 /* set the pci address in s->config_reg */ 578 phb->config_reg = (pciaddr) | (1u << 31); 579 580 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 581 status = pci_get_word(d->config + PCI_STATUS); 582 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 583 pci_set_word(d->config + PCI_STATUS, status); 584 585 return pci_data_read(phb->bus, phb->config_reg, 2); 586 } 587 588 static uint32_t bonito_spciconf_readl(void *opaque, hwaddr addr) 589 { 590 PCIBonitoState *s = opaque; 591 PCIDevice *d = PCI_DEVICE(s); 592 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 593 uint32_t pciaddr; 594 uint16_t status; 595 596 DPRINTF("bonito_spciconf_readl "TARGET_FMT_plx"\n", addr); 597 assert((addr & 0x3) == 0); 598 599 pciaddr = bonito_sbridge_pciaddr(s, addr); 600 601 if (pciaddr == 0xffffffff) { 602 return 0xffffffff; 603 } 604 605 /* set the pci address in s->config_reg */ 606 phb->config_reg = (pciaddr) | (1u << 31); 607 608 /* clear PCI_STATUS_REC_MASTER_ABORT and PCI_STATUS_REC_TARGET_ABORT */ 609 status = pci_get_word(d->config + PCI_STATUS); 610 status &= ~(PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT); 611 pci_set_word(d->config + PCI_STATUS, status); 612 613 return pci_data_read(phb->bus, phb->config_reg, 4); 614 } 615 616 /* south bridge PCI configure space. 0x1fe8 0000 - 0x1fef ffff */ 617 static const MemoryRegionOps bonito_spciconf_ops = { 618 .old_mmio = { 619 .read = { 620 bonito_spciconf_readb, 621 bonito_spciconf_readw, 622 bonito_spciconf_readl, 623 }, 624 .write = { 625 bonito_spciconf_writeb, 626 bonito_spciconf_writew, 627 bonito_spciconf_writel, 628 }, 629 }, 630 .endianness = DEVICE_NATIVE_ENDIAN, 631 }; 632 633 #define BONITO_IRQ_BASE 32 634 635 static void pci_bonito_set_irq(void *opaque, int irq_num, int level) 636 { 637 BonitoState *s = opaque; 638 qemu_irq *pic = s->pic; 639 PCIBonitoState *bonito_state = s->pci_dev; 640 int internal_irq = irq_num - BONITO_IRQ_BASE; 641 642 if (bonito_state->regs[BONITO_INTEDGE] & (1 << internal_irq)) { 643 qemu_irq_pulse(*pic); 644 } else { /* level triggered */ 645 if (bonito_state->regs[BONITO_INTPOL] & (1 << internal_irq)) { 646 qemu_irq_raise(*pic); 647 } else { 648 qemu_irq_lower(*pic); 649 } 650 } 651 } 652 653 /* map the original irq (0~3) to bonito irq (16~47, but 16~31 are unused) */ 654 static int pci_bonito_map_irq(PCIDevice * pci_dev, int irq_num) 655 { 656 int slot; 657 658 slot = (pci_dev->devfn >> 3); 659 660 switch (slot) { 661 case 5: /* FULONG2E_VIA_SLOT, SouthBridge, IDE, USB, ACPI, AC97, MC97 */ 662 return irq_num % 4 + BONITO_IRQ_BASE; 663 case 6: /* FULONG2E_ATI_SLOT, VGA */ 664 return 4 + BONITO_IRQ_BASE; 665 case 7: /* FULONG2E_RTL_SLOT, RTL8139 */ 666 return 5 + BONITO_IRQ_BASE; 667 case 8 ... 12: /* PCI slot 1 to 4 */ 668 return (slot - 8 + irq_num) + 6 + BONITO_IRQ_BASE; 669 default: /* Unknown device, don't do any translation */ 670 return irq_num; 671 } 672 } 673 674 static void bonito_reset(void *opaque) 675 { 676 PCIBonitoState *s = opaque; 677 678 /* set the default value of north bridge registers */ 679 680 s->regs[BONITO_BONPONCFG] = 0xc40; 681 s->regs[BONITO_BONGENCFG] = 0x1384; 682 s->regs[BONITO_IODEVCFG] = 0x2bff8010; 683 s->regs[BONITO_SDCFG] = 0x255e0091; 684 685 s->regs[BONITO_GPIODATA] = 0x1ff; 686 s->regs[BONITO_GPIOIE] = 0x1ff; 687 s->regs[BONITO_DQCFG] = 0x8; 688 s->regs[BONITO_MEMSIZE] = 0x10000000; 689 s->regs[BONITO_PCIMAP] = 0x6140; 690 } 691 692 static const VMStateDescription vmstate_bonito = { 693 .name = "Bonito", 694 .version_id = 1, 695 .minimum_version_id = 1, 696 .minimum_version_id_old = 1, 697 .fields = (VMStateField []) { 698 VMSTATE_PCI_DEVICE(dev, PCIBonitoState), 699 VMSTATE_END_OF_LIST() 700 } 701 }; 702 703 static int bonito_pcihost_initfn(SysBusDevice *dev) 704 { 705 PCIHostState *phb = PCI_HOST_BRIDGE(dev); 706 707 phb->bus = pci_register_bus(DEVICE(dev), "pci", 708 pci_bonito_set_irq, pci_bonito_map_irq, dev, 709 get_system_memory(), get_system_io(), 710 0x28, 32, TYPE_PCI_BUS); 711 712 return 0; 713 } 714 715 static int bonito_initfn(PCIDevice *dev) 716 { 717 PCIBonitoState *s = DO_UPCAST(PCIBonitoState, dev, dev); 718 SysBusDevice *sysbus = SYS_BUS_DEVICE(s->pcihost); 719 PCIHostState *phb = PCI_HOST_BRIDGE(s->pcihost); 720 721 /* Bonito North Bridge, built on FPGA, VENDOR_ID/DEVICE_ID are "undefined" */ 722 pci_config_set_prog_interface(dev->config, 0x00); 723 724 /* set the north bridge register mapping */ 725 memory_region_init_io(&s->iomem, NULL, &bonito_ops, s, 726 "north-bridge-register", BONITO_INTERNAL_REG_SIZE); 727 sysbus_init_mmio(sysbus, &s->iomem); 728 sysbus_mmio_map(sysbus, 0, BONITO_INTERNAL_REG_BASE); 729 730 /* set the north bridge pci configure mapping */ 731 memory_region_init_io(&phb->conf_mem, NULL, &bonito_pciconf_ops, s, 732 "north-bridge-pci-config", BONITO_PCICONFIG_SIZE); 733 sysbus_init_mmio(sysbus, &phb->conf_mem); 734 sysbus_mmio_map(sysbus, 1, BONITO_PCICONFIG_BASE); 735 736 /* set the south bridge pci configure mapping */ 737 memory_region_init_io(&phb->data_mem, NULL, &bonito_spciconf_ops, s, 738 "south-bridge-pci-config", BONITO_SPCICONFIG_SIZE); 739 sysbus_init_mmio(sysbus, &phb->data_mem); 740 sysbus_mmio_map(sysbus, 2, BONITO_SPCICONFIG_BASE); 741 742 memory_region_init_io(&s->iomem_ldma, NULL, &bonito_ldma_ops, s, 743 "ldma", 0x100); 744 sysbus_init_mmio(sysbus, &s->iomem_ldma); 745 sysbus_mmio_map(sysbus, 3, 0xbfe00200); 746 747 memory_region_init_io(&s->iomem_cop, NULL, &bonito_cop_ops, s, 748 "cop", 0x100); 749 sysbus_init_mmio(sysbus, &s->iomem_cop); 750 sysbus_mmio_map(sysbus, 4, 0xbfe00300); 751 752 /* Map PCI IO Space 0x1fd0 0000 - 0x1fd1 0000 */ 753 s->bonito_pciio_start = BONITO_PCIIO_BASE; 754 s->bonito_pciio_length = BONITO_PCIIO_SIZE; 755 isa_mem_base = s->bonito_pciio_start; 756 isa_mmio_init(s->bonito_pciio_start, s->bonito_pciio_length); 757 758 /* add pci local io mapping */ 759 s->bonito_localio_start = BONITO_DEV_BASE; 760 s->bonito_localio_length = BONITO_DEV_SIZE; 761 isa_mmio_init(s->bonito_localio_start, s->bonito_localio_length); 762 763 /* set the default value of north bridge pci config */ 764 pci_set_word(dev->config + PCI_COMMAND, 0x0000); 765 pci_set_word(dev->config + PCI_STATUS, 0x0000); 766 pci_set_word(dev->config + PCI_SUBSYSTEM_VENDOR_ID, 0x0000); 767 pci_set_word(dev->config + PCI_SUBSYSTEM_ID, 0x0000); 768 769 pci_set_byte(dev->config + PCI_INTERRUPT_LINE, 0x00); 770 pci_set_byte(dev->config + PCI_INTERRUPT_PIN, 0x01); 771 pci_set_byte(dev->config + PCI_MIN_GNT, 0x3c); 772 pci_set_byte(dev->config + PCI_MAX_LAT, 0x00); 773 774 qemu_register_reset(bonito_reset, s); 775 776 return 0; 777 } 778 779 PCIBus *bonito_init(qemu_irq *pic) 780 { 781 DeviceState *dev; 782 BonitoState *pcihost; 783 PCIHostState *phb; 784 PCIBonitoState *s; 785 PCIDevice *d; 786 787 dev = qdev_create(NULL, TYPE_BONITO_PCI_HOST_BRIDGE); 788 phb = PCI_HOST_BRIDGE(dev); 789 pcihost = BONITO_PCI_HOST_BRIDGE(dev); 790 pcihost->pic = pic; 791 qdev_init_nofail(dev); 792 793 /* set the pcihost pointer before bonito_initfn is called */ 794 d = pci_create(phb->bus, PCI_DEVFN(0, 0), "Bonito"); 795 s = DO_UPCAST(PCIBonitoState, dev, d); 796 s->pcihost = pcihost; 797 pcihost->pci_dev = s; 798 qdev_init_nofail(DEVICE(d)); 799 800 return phb->bus; 801 } 802 803 static void bonito_class_init(ObjectClass *klass, void *data) 804 { 805 DeviceClass *dc = DEVICE_CLASS(klass); 806 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 807 808 k->init = bonito_initfn; 809 k->vendor_id = 0xdf53; 810 k->device_id = 0x00d5; 811 k->revision = 0x01; 812 k->class_id = PCI_CLASS_BRIDGE_HOST; 813 dc->desc = "Host bridge"; 814 dc->no_user = 1; 815 dc->vmsd = &vmstate_bonito; 816 } 817 818 static const TypeInfo bonito_info = { 819 .name = "Bonito", 820 .parent = TYPE_PCI_DEVICE, 821 .instance_size = sizeof(PCIBonitoState), 822 .class_init = bonito_class_init, 823 }; 824 825 static void bonito_pcihost_class_init(ObjectClass *klass, void *data) 826 { 827 DeviceClass *dc = DEVICE_CLASS(klass); 828 SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass); 829 830 k->init = bonito_pcihost_initfn; 831 dc->no_user = 1; 832 } 833 834 static const TypeInfo bonito_pcihost_info = { 835 .name = TYPE_BONITO_PCI_HOST_BRIDGE, 836 .parent = TYPE_PCI_HOST_BRIDGE, 837 .instance_size = sizeof(BonitoState), 838 .class_init = bonito_pcihost_class_init, 839 }; 840 841 static void bonito_register_types(void) 842 { 843 type_register_static(&bonito_pcihost_info); 844 type_register_static(&bonito_info); 845 } 846 847 type_init(bonito_register_types) 848