1 /*
2 * Mai Logic Articia S emulation
3 *
4 * Copyright (c) 2023 BALATON Zoltan
5 *
6 * This work is licensed under the GNU GPL license version 2 or later.
7 *
8 */
9
10 #include "qemu/osdep.h"
11 #include "qemu/log.h"
12 #include "qapi/error.h"
13 #include "hw/pci/pci_device.h"
14 #include "hw/pci/pci_host.h"
15 #include "hw/irq.h"
16 #include "hw/i2c/bitbang_i2c.h"
17 #include "hw/intc/i8259.h"
18 #include "hw/pci-host/articia.h"
19
20 /*
21 * This is a minimal emulation of this chip as used in AmigaOne board.
22 * Most features are missing but those are not needed by firmware and guests.
23 */
24
25 OBJECT_DECLARE_SIMPLE_TYPE(ArticiaState, ARTICIA)
26
27 OBJECT_DECLARE_SIMPLE_TYPE(ArticiaHostState, ARTICIA_PCI_HOST)
28 struct ArticiaHostState {
29 PCIDevice parent_obj;
30
31 ArticiaState *as;
32 };
33
34 /* TYPE_ARTICIA */
35
36 struct ArticiaState {
37 PCIHostState parent_obj;
38
39 qemu_irq irq[PCI_NUM_PINS];
40 MemoryRegion io;
41 MemoryRegion mem;
42 MemoryRegion reg;
43
44 bitbang_i2c_interface smbus;
45 uint32_t gpio; /* bits 0-7 in, 8-15 out, 16-23 direction (0 in, 1 out) */
46 hwaddr gpio_base;
47 MemoryRegion gpio_reg;
48 };
49
articia_gpio_read(void * opaque,hwaddr addr,unsigned int size)50 static uint64_t articia_gpio_read(void *opaque, hwaddr addr, unsigned int size)
51 {
52 ArticiaState *s = opaque;
53
54 return (s->gpio >> (addr * 8)) & 0xff;
55 }
56
articia_gpio_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)57 static void articia_gpio_write(void *opaque, hwaddr addr, uint64_t val,
58 unsigned int size)
59 {
60 ArticiaState *s = opaque;
61 uint32_t sh = addr * 8;
62
63 if (addr == 0) {
64 /* in bits read only? */
65 return;
66 }
67
68 if ((s->gpio & (0xff << sh)) != (val & 0xff) << sh) {
69 s->gpio &= ~(0xff << sh | 0xff);
70 s->gpio |= (val & 0xff) << sh;
71 s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SDA,
72 s->gpio & BIT(16) ?
73 !!(s->gpio & BIT(8)) : 1);
74 if ((s->gpio & BIT(17))) {
75 s->gpio &= ~BIT(0);
76 s->gpio |= bitbang_i2c_set(&s->smbus, BITBANG_I2C_SCL,
77 !!(s->gpio & BIT(9)));
78 }
79 }
80 }
81
82 static const MemoryRegionOps articia_gpio_ops = {
83 .read = articia_gpio_read,
84 .write = articia_gpio_write,
85 .valid.min_access_size = 1,
86 .valid.max_access_size = 1,
87 .endianness = DEVICE_LITTLE_ENDIAN,
88 };
89
articia_reg_read(void * opaque,hwaddr addr,unsigned int size)90 static uint64_t articia_reg_read(void *opaque, hwaddr addr, unsigned int size)
91 {
92 ArticiaState *s = opaque;
93 uint64_t ret = UINT_MAX;
94
95 switch (addr) {
96 case 0xc00cf8:
97 ret = pci_host_conf_le_ops.read(PCI_HOST_BRIDGE(s), 0, size);
98 break;
99 case 0xe00cfc ... 0xe00cff:
100 ret = pci_host_data_le_ops.read(PCI_HOST_BRIDGE(s), addr - 0xe00cfc, size);
101 break;
102 case 0xf00000:
103 ret = pic_read_irq(isa_pic);
104 break;
105 default:
106 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register read 0x%"
107 HWADDR_PRIx " %d\n", __func__, addr, size);
108 break;
109 }
110 return ret;
111 }
112
articia_reg_write(void * opaque,hwaddr addr,uint64_t val,unsigned int size)113 static void articia_reg_write(void *opaque, hwaddr addr, uint64_t val,
114 unsigned int size)
115 {
116 ArticiaState *s = opaque;
117
118 switch (addr) {
119 case 0xc00cf8:
120 pci_host_conf_le_ops.write(PCI_HOST_BRIDGE(s), 0, val, size);
121 break;
122 case 0xe00cfc ... 0xe00cff:
123 pci_host_data_le_ops.write(PCI_HOST_BRIDGE(s), addr, val, size);
124 break;
125 default:
126 qemu_log_mask(LOG_UNIMP, "%s: Unimplemented register write 0x%"
127 HWADDR_PRIx " %d <- %"PRIx64"\n", __func__, addr, size, val);
128 break;
129 }
130 }
131
132 static const MemoryRegionOps articia_reg_ops = {
133 .read = articia_reg_read,
134 .write = articia_reg_write,
135 .valid.min_access_size = 1,
136 .valid.max_access_size = 4,
137 .endianness = DEVICE_LITTLE_ENDIAN,
138 };
139
articia_pcihost_set_irq(void * opaque,int n,int level)140 static void articia_pcihost_set_irq(void *opaque, int n, int level)
141 {
142 ArticiaState *s = opaque;
143 qemu_set_irq(s->irq[n], level);
144 }
145
146 /*
147 * AmigaOne SE PCI slot to IRQ routing
148 *
149 * repository: https://source.denx.de/u-boot/custodians/u-boot-avr32.git
150 * refspec: v2010.06
151 * file: board/MAI/AmigaOneG3SE/articiaS_pci.c
152 */
amigaone_pcihost_bus0_map_irq(PCIDevice * pdev,int pin)153 static int amigaone_pcihost_bus0_map_irq(PCIDevice *pdev, int pin)
154 {
155 int devfn_slot = PCI_SLOT(pdev->devfn);
156
157 switch (devfn_slot) {
158 case 6: /* On board ethernet */
159 return 3;
160 case 7: /* South bridge */
161 return pin;
162 default: /* PCI Slot 1 Devfn slot 8, Slot 2 Devfn 9, Slot 3 Devfn 10 */
163 return pci_swizzle(devfn_slot, pin);
164 }
165
166 }
167
articia_realize(DeviceState * dev,Error ** errp)168 static void articia_realize(DeviceState *dev, Error **errp)
169 {
170 ArticiaState *s = ARTICIA(dev);
171 PCIHostState *h = PCI_HOST_BRIDGE(dev);
172 PCIDevice *pdev;
173
174 bitbang_i2c_init(&s->smbus, i2c_init_bus(dev, "smbus"));
175 memory_region_init_io(&s->gpio_reg, OBJECT(s), &articia_gpio_ops, s,
176 TYPE_ARTICIA, 4);
177
178 memory_region_init(&s->mem, OBJECT(dev), "pci-mem", UINT64_MAX);
179 memory_region_init(&s->io, OBJECT(dev), "pci-io", 0xc00000);
180 memory_region_init_io(&s->reg, OBJECT(s), &articia_reg_ops, s,
181 TYPE_ARTICIA, 0x1000000);
182 memory_region_add_subregion_overlap(&s->reg, 0, &s->io, 1);
183
184 /* devfn_min is 8 that matches first PCI slot in AmigaOne */
185 h->bus = pci_register_root_bus(dev, NULL, articia_pcihost_set_irq,
186 amigaone_pcihost_bus0_map_irq, dev, &s->mem,
187 &s->io, PCI_DEVFN(8, 0), 4, TYPE_PCI_BUS);
188 pdev = pci_create_simple_multifunction(h->bus, PCI_DEVFN(0, 0),
189 TYPE_ARTICIA_PCI_HOST);
190 ARTICIA_PCI_HOST(pdev)->as = s;
191 pci_create_simple(h->bus, PCI_DEVFN(0, 1), TYPE_ARTICIA_PCI_BRIDGE);
192
193 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->reg);
194 sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mem);
195 qdev_init_gpio_out(dev, s->irq, ARRAY_SIZE(s->irq));
196 }
197
articia_class_init(ObjectClass * klass,void * data)198 static void articia_class_init(ObjectClass *klass, void *data)
199 {
200 DeviceClass *dc = DEVICE_CLASS(klass);
201
202 dc->realize = articia_realize;
203 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
204 }
205
206 /* TYPE_ARTICIA_PCI_HOST */
207
articia_pci_host_cfg_write(PCIDevice * d,uint32_t addr,uint32_t val,int len)208 static void articia_pci_host_cfg_write(PCIDevice *d, uint32_t addr,
209 uint32_t val, int len)
210 {
211 ArticiaState *s = ARTICIA_PCI_HOST(d)->as;
212
213 pci_default_write_config(d, addr, val, len);
214 switch (addr) {
215 case 0x40:
216 s->gpio_base = val;
217 break;
218 case 0x44:
219 if (val != 0x11) {
220 /* FIXME what do the bits actually mean? */
221 break;
222 }
223 if (memory_region_is_mapped(&s->gpio_reg)) {
224 memory_region_del_subregion(&s->io, &s->gpio_reg);
225 }
226 memory_region_add_subregion(&s->io, s->gpio_base + 0x38, &s->gpio_reg);
227 break;
228 }
229 }
230
articia_pci_host_class_init(ObjectClass * klass,void * data)231 static void articia_pci_host_class_init(ObjectClass *klass, void *data)
232 {
233 DeviceClass *dc = DEVICE_CLASS(klass);
234 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
235
236 k->config_write = articia_pci_host_cfg_write;
237 k->vendor_id = 0x10cc;
238 k->device_id = 0x0660;
239 k->class_id = PCI_CLASS_BRIDGE_HOST;
240 /*
241 * PCI-facing part of the host bridge,
242 * not usable without the host-facing part
243 */
244 dc->user_creatable = false;
245 }
246
247 /* TYPE_ARTICIA_PCI_BRIDGE */
248
articia_pci_bridge_class_init(ObjectClass * klass,void * data)249 static void articia_pci_bridge_class_init(ObjectClass *klass, void *data)
250 {
251 DeviceClass *dc = DEVICE_CLASS(klass);
252 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
253
254 k->vendor_id = 0x10cc;
255 k->device_id = 0x0661;
256 k->class_id = PCI_CLASS_BRIDGE_HOST;
257 /*
258 * PCI-facing part of the host bridge,
259 * not usable without the host-facing part
260 */
261 dc->user_creatable = false;
262 }
263
264 static const TypeInfo articia_types[] = {
265 {
266 .name = TYPE_ARTICIA,
267 .parent = TYPE_PCI_HOST_BRIDGE,
268 .instance_size = sizeof(ArticiaState),
269 .class_init = articia_class_init,
270 },
271 {
272 .name = TYPE_ARTICIA_PCI_HOST,
273 .parent = TYPE_PCI_DEVICE,
274 .instance_size = sizeof(ArticiaHostState),
275 .class_init = articia_pci_host_class_init,
276 .interfaces = (InterfaceInfo[]) {
277 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
278 { },
279 },
280 },
281 {
282 .name = TYPE_ARTICIA_PCI_BRIDGE,
283 .parent = TYPE_PCI_DEVICE,
284 .instance_size = sizeof(PCIDevice),
285 .class_init = articia_pci_bridge_class_init,
286 .interfaces = (InterfaceInfo[]) {
287 { INTERFACE_CONVENTIONAL_PCI_DEVICE },
288 { },
289 },
290 },
291 };
292
293 DEFINE_TYPES(articia_types)
294