1 /* 2 * xio3130_upstream.c 3 * TI X3130 pci express upstream port switch 4 * 5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "hw/pci/pci_ids.h" 23 #include "hw/pci/msi.h" 24 #include "hw/pci/pcie.h" 25 #include "xio3130_upstream.h" 26 27 #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ 28 #define XIO3130_REVISION 0x2 29 #define XIO3130_MSI_OFFSET 0x70 30 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT 31 #define XIO3130_MSI_NR_VECTOR 1 32 #define XIO3130_SSVID_OFFSET 0x80 33 #define XIO3130_SSVID_SVID 0 34 #define XIO3130_SSVID_SSID 0 35 #define XIO3130_EXP_OFFSET 0x90 36 #define XIO3130_AER_OFFSET 0x100 37 38 static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, 39 uint32_t val, int len) 40 { 41 pci_bridge_write_config(d, address, val, len); 42 pcie_cap_flr_write_config(d, address, val, len); 43 pcie_aer_write_config(d, address, val, len); 44 } 45 46 static void xio3130_upstream_reset(DeviceState *qdev) 47 { 48 PCIDevice *d = PCI_DEVICE(qdev); 49 50 pci_bridge_reset(qdev); 51 pcie_cap_deverr_reset(d); 52 } 53 54 static int xio3130_upstream_initfn(PCIDevice *d) 55 { 56 PCIEPort *p = PCIE_PORT(d); 57 int rc; 58 59 rc = pci_bridge_initfn(d, TYPE_PCIE_BUS); 60 if (rc < 0) { 61 return rc; 62 } 63 64 pcie_port_init_reg(d); 65 66 rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, 67 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 68 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT); 69 if (rc < 0) { 70 goto err_bridge; 71 } 72 rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, 73 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID); 74 if (rc < 0) { 75 goto err_bridge; 76 } 77 rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, 78 p->port); 79 if (rc < 0) { 80 goto err_msi; 81 } 82 pcie_cap_flr_init(d); 83 pcie_cap_deverr_init(d); 84 rc = pcie_aer_init(d, XIO3130_AER_OFFSET); 85 if (rc < 0) { 86 goto err; 87 } 88 89 return 0; 90 91 err: 92 pcie_cap_exit(d); 93 err_msi: 94 msi_uninit(d); 95 err_bridge: 96 pci_bridge_exitfn(d); 97 return rc; 98 } 99 100 static void xio3130_upstream_exitfn(PCIDevice *d) 101 { 102 pcie_aer_exit(d); 103 pcie_cap_exit(d); 104 msi_uninit(d); 105 pci_bridge_exitfn(d); 106 } 107 108 PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, 109 const char *bus_name, pci_map_irq_fn map_irq, 110 uint8_t port) 111 { 112 PCIDevice *d; 113 PCIBridge *br; 114 DeviceState *qdev; 115 116 d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream"); 117 if (!d) { 118 return NULL; 119 } 120 br = PCI_BRIDGE(d); 121 122 qdev = DEVICE(d); 123 pci_bridge_map_irq(br, bus_name, map_irq); 124 qdev_prop_set_uint8(qdev, "port", port); 125 qdev_init_nofail(qdev); 126 127 return PCIE_PORT(d); 128 } 129 130 static const VMStateDescription vmstate_xio3130_upstream = { 131 .name = "xio3130-express-upstream-port", 132 .version_id = 1, 133 .minimum_version_id = 1, 134 .fields = (VMStateField[]) { 135 VMSTATE_PCIE_DEVICE(parent_obj.parent_obj, PCIEPort), 136 VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0, 137 vmstate_pcie_aer_log, PCIEAERLog), 138 VMSTATE_END_OF_LIST() 139 } 140 }; 141 142 static void xio3130_upstream_class_init(ObjectClass *klass, void *data) 143 { 144 DeviceClass *dc = DEVICE_CLASS(klass); 145 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 146 147 k->is_express = 1; 148 k->is_bridge = 1; 149 k->config_write = xio3130_upstream_write_config; 150 k->init = xio3130_upstream_initfn; 151 k->exit = xio3130_upstream_exitfn; 152 k->vendor_id = PCI_VENDOR_ID_TI; 153 k->device_id = PCI_DEVICE_ID_TI_XIO3130U; 154 k->revision = XIO3130_REVISION; 155 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 156 dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; 157 dc->reset = xio3130_upstream_reset; 158 dc->vmsd = &vmstate_xio3130_upstream; 159 } 160 161 static const TypeInfo xio3130_upstream_info = { 162 .name = "x3130-upstream", 163 .parent = TYPE_PCIE_PORT, 164 .class_init = xio3130_upstream_class_init, 165 }; 166 167 static void xio3130_upstream_register_types(void) 168 { 169 type_register_static(&xio3130_upstream_info); 170 } 171 172 type_init(xio3130_upstream_register_types) 173 174 175 /* 176 * Local variables: 177 * c-indent-level: 4 178 * c-basic-offset: 4 179 * tab-width: 8 180 * indent-tab-mode: nil 181 * End: 182 */ 183