1 /* 2 * xio3130_upstream.c 3 * TI X3130 pci express upstream port switch 4 * 5 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 6 * VA Linux Systems Japan K.K. 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License as published by 10 * the Free Software Foundation; either version 2 of the License, or 11 * (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License along 19 * with this program; if not, see <http://www.gnu.org/licenses/>. 20 */ 21 22 #include "qemu/osdep.h" 23 #include "hw/pci/pci_ids.h" 24 #include "hw/pci/msi.h" 25 #include "hw/pci/pcie.h" 26 #include "xio3130_upstream.h" 27 28 #define PCI_DEVICE_ID_TI_XIO3130U 0x8232 /* upstream port */ 29 #define XIO3130_REVISION 0x2 30 #define XIO3130_MSI_OFFSET 0x70 31 #define XIO3130_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_64BIT 32 #define XIO3130_MSI_NR_VECTOR 1 33 #define XIO3130_SSVID_OFFSET 0x80 34 #define XIO3130_SSVID_SVID 0 35 #define XIO3130_SSVID_SSID 0 36 #define XIO3130_EXP_OFFSET 0x90 37 #define XIO3130_AER_OFFSET 0x100 38 39 static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address, 40 uint32_t val, int len) 41 { 42 pci_bridge_write_config(d, address, val, len); 43 pcie_cap_flr_write_config(d, address, val, len); 44 pcie_aer_write_config(d, address, val, len); 45 } 46 47 static void xio3130_upstream_reset(DeviceState *qdev) 48 { 49 PCIDevice *d = PCI_DEVICE(qdev); 50 51 pci_bridge_reset(qdev); 52 pcie_cap_deverr_reset(d); 53 } 54 55 static void xio3130_upstream_realize(PCIDevice *d, Error **errp) 56 { 57 PCIEPort *p = PCIE_PORT(d); 58 int rc; 59 60 pci_bridge_initfn(d, TYPE_PCIE_BUS); 61 pcie_port_init_reg(d); 62 63 rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR, 64 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 65 XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, 66 errp); 67 if (rc < 0) { 68 assert(rc == -ENOTSUP); 69 goto err_bridge; 70 } 71 72 rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET, 73 XIO3130_SSVID_SVID, XIO3130_SSVID_SSID, 74 errp); 75 if (rc < 0) { 76 goto err_bridge; 77 } 78 79 rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_UPSTREAM, 80 p->port, errp); 81 if (rc < 0) { 82 goto err_msi; 83 } 84 pcie_cap_flr_init(d); 85 pcie_cap_deverr_init(d); 86 87 rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET, 88 PCI_ERR_SIZEOF, errp); 89 if (rc < 0) { 90 goto err; 91 } 92 93 return; 94 95 err: 96 pcie_cap_exit(d); 97 err_msi: 98 msi_uninit(d); 99 err_bridge: 100 pci_bridge_exitfn(d); 101 } 102 103 static void xio3130_upstream_exitfn(PCIDevice *d) 104 { 105 pcie_aer_exit(d); 106 pcie_cap_exit(d); 107 msi_uninit(d); 108 pci_bridge_exitfn(d); 109 } 110 111 PCIEPort *xio3130_upstream_init(PCIBus *bus, int devfn, bool multifunction, 112 const char *bus_name, pci_map_irq_fn map_irq, 113 uint8_t port) 114 { 115 PCIDevice *d; 116 PCIBridge *br; 117 DeviceState *qdev; 118 119 d = pci_create_multifunction(bus, devfn, multifunction, "x3130-upstream"); 120 if (!d) { 121 return NULL; 122 } 123 br = PCI_BRIDGE(d); 124 125 qdev = DEVICE(d); 126 pci_bridge_map_irq(br, bus_name, map_irq); 127 qdev_prop_set_uint8(qdev, "port", port); 128 qdev_init_nofail(qdev); 129 130 return PCIE_PORT(d); 131 } 132 133 static const VMStateDescription vmstate_xio3130_upstream = { 134 .name = "xio3130-express-upstream-port", 135 .priority = MIG_PRI_PCI_BUS, 136 .version_id = 1, 137 .minimum_version_id = 1, 138 .fields = (VMStateField[]) { 139 VMSTATE_PCI_DEVICE(parent_obj.parent_obj, PCIEPort), 140 VMSTATE_STRUCT(parent_obj.parent_obj.exp.aer_log, PCIEPort, 0, 141 vmstate_pcie_aer_log, PCIEAERLog), 142 VMSTATE_END_OF_LIST() 143 } 144 }; 145 146 static void xio3130_upstream_class_init(ObjectClass *klass, void *data) 147 { 148 DeviceClass *dc = DEVICE_CLASS(klass); 149 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 150 151 k->is_bridge = 1; 152 k->config_write = xio3130_upstream_write_config; 153 k->realize = xio3130_upstream_realize; 154 k->exit = xio3130_upstream_exitfn; 155 k->vendor_id = PCI_VENDOR_ID_TI; 156 k->device_id = PCI_DEVICE_ID_TI_XIO3130U; 157 k->revision = XIO3130_REVISION; 158 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 159 dc->desc = "TI X3130 Upstream Port of PCI Express Switch"; 160 dc->reset = xio3130_upstream_reset; 161 dc->vmsd = &vmstate_xio3130_upstream; 162 } 163 164 static const TypeInfo xio3130_upstream_info = { 165 .name = "x3130-upstream", 166 .parent = TYPE_PCIE_PORT, 167 .class_init = xio3130_upstream_class_init, 168 .interfaces = (InterfaceInfo[]) { 169 { INTERFACE_PCIE_DEVICE }, 170 { } 171 }, 172 }; 173 174 static void xio3130_upstream_register_types(void) 175 { 176 type_register_static(&xio3130_upstream_info); 177 } 178 179 type_init(xio3130_upstream_register_types) 180