1 /*
2  * x3130_downstream.c
3  * TI X3130 pci express downstream port switch
4  *
5  * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
6  *                    VA Linux Systems Japan K.K.
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #include "qemu/osdep.h"
23 #include "hw/pci/pci_ids.h"
24 #include "hw/pci/msi.h"
25 #include "hw/pci/pcie.h"
26 #include "hw/pci/pcie_port.h"
27 #include "qapi/error.h"
28 #include "qemu/module.h"
29 
30 #define PCI_DEVICE_ID_TI_XIO3130D       0x8233  /* downstream port */
31 #define XIO3130_REVISION                0x1
32 #define XIO3130_MSI_OFFSET              0x70
33 #define XIO3130_MSI_SUPPORTED_FLAGS     PCI_MSI_FLAGS_64BIT
34 #define XIO3130_MSI_NR_VECTOR           1
35 #define XIO3130_SSVID_OFFSET            0x80
36 #define XIO3130_SSVID_SVID              0
37 #define XIO3130_SSVID_SSID              0
38 #define XIO3130_EXP_OFFSET              0x90
39 #define XIO3130_AER_OFFSET              0x100
40 
41 static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
42                                          uint32_t val, int len)
43 {
44     uint16_t slt_ctl, slt_sta;
45 
46     pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
47     pci_bridge_write_config(d, address, val, len);
48     pcie_cap_flr_write_config(d, address, val, len);
49     pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
50     pcie_aer_write_config(d, address, val, len);
51 }
52 
53 static void xio3130_downstream_reset(DeviceState *qdev)
54 {
55     PCIDevice *d = PCI_DEVICE(qdev);
56 
57     pcie_cap_deverr_reset(d);
58     pcie_cap_slot_reset(d);
59     pcie_cap_arifwd_reset(d);
60     pci_bridge_reset(qdev);
61 }
62 
63 static void xio3130_downstream_realize(PCIDevice *d, Error **errp)
64 {
65     PCIEPort *p = PCIE_PORT(d);
66     PCIESlot *s = PCIE_SLOT(d);
67     int rc;
68 
69     pci_bridge_initfn(d, TYPE_PCIE_BUS);
70     pcie_port_init_reg(d);
71 
72     rc = msi_init(d, XIO3130_MSI_OFFSET, XIO3130_MSI_NR_VECTOR,
73                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT,
74                   XIO3130_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT,
75                   errp);
76     if (rc < 0) {
77         assert(rc == -ENOTSUP);
78         goto err_bridge;
79     }
80 
81     rc = pci_bridge_ssvid_init(d, XIO3130_SSVID_OFFSET,
82                                XIO3130_SSVID_SVID, XIO3130_SSVID_SSID,
83                                errp);
84     if (rc < 0) {
85         goto err_bridge;
86     }
87 
88     rc = pcie_cap_init(d, XIO3130_EXP_OFFSET, PCI_EXP_TYPE_DOWNSTREAM,
89                        p->port, errp);
90     if (rc < 0) {
91         goto err_msi;
92     }
93     pcie_cap_flr_init(d);
94     pcie_cap_deverr_init(d);
95     pcie_cap_slot_init(d, s->slot);
96     pcie_cap_arifwd_init(d);
97 
98     pcie_chassis_create(s->chassis);
99     rc = pcie_chassis_add_slot(s);
100     if (rc < 0) {
101         error_setg(errp, "Can't add chassis slot, error %d", rc);
102         goto err_pcie_cap;
103     }
104 
105     rc = pcie_aer_init(d, PCI_ERR_VER, XIO3130_AER_OFFSET,
106                        PCI_ERR_SIZEOF, errp);
107     if (rc < 0) {
108         goto err;
109     }
110 
111     return;
112 
113 err:
114     pcie_chassis_del_slot(s);
115 err_pcie_cap:
116     pcie_cap_exit(d);
117 err_msi:
118     msi_uninit(d);
119 err_bridge:
120     pci_bridge_exitfn(d);
121 }
122 
123 static void xio3130_downstream_exitfn(PCIDevice *d)
124 {
125     PCIESlot *s = PCIE_SLOT(d);
126 
127     pcie_aer_exit(d);
128     pcie_chassis_del_slot(s);
129     pcie_cap_exit(d);
130     msi_uninit(d);
131     pci_bridge_exitfn(d);
132 }
133 
134 static Property xio3130_downstream_props[] = {
135     DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present,
136                     QEMU_PCIE_SLTCAP_PCP_BITNR, true),
137     DEFINE_PROP_END_OF_LIST()
138 };
139 
140 static const VMStateDescription vmstate_xio3130_downstream = {
141     .name = "xio3130-express-downstream-port",
142     .priority = MIG_PRI_PCI_BUS,
143     .version_id = 1,
144     .minimum_version_id = 1,
145     .post_load = pcie_cap_slot_post_load,
146     .fields = (VMStateField[]) {
147         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
148         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
149                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
150         VMSTATE_END_OF_LIST()
151     }
152 };
153 
154 static void xio3130_downstream_class_init(ObjectClass *klass, void *data)
155 {
156     DeviceClass *dc = DEVICE_CLASS(klass);
157     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
158 
159     k->is_bridge = true;
160     k->config_write = xio3130_downstream_write_config;
161     k->realize = xio3130_downstream_realize;
162     k->exit = xio3130_downstream_exitfn;
163     k->vendor_id = PCI_VENDOR_ID_TI;
164     k->device_id = PCI_DEVICE_ID_TI_XIO3130D;
165     k->revision = XIO3130_REVISION;
166     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
167     dc->desc = "TI X3130 Downstream Port of PCI Express Switch";
168     dc->reset = xio3130_downstream_reset;
169     dc->vmsd = &vmstate_xio3130_downstream;
170     dc->props = xio3130_downstream_props;
171 }
172 
173 static const TypeInfo xio3130_downstream_info = {
174     .name          = "xio3130-downstream",
175     .parent        = TYPE_PCIE_SLOT,
176     .class_init    = xio3130_downstream_class_init,
177     .interfaces = (InterfaceInfo[]) {
178         { INTERFACE_PCIE_DEVICE },
179         { }
180     },
181 };
182 
183 static void xio3130_downstream_register_types(void)
184 {
185     type_register_static(&xio3130_downstream_info);
186 }
187 
188 type_init(xio3130_downstream_register_types)
189