1 /* 2 * QEMU Simba PCI bridge 3 * 4 * Copyright (c) 2006 Fabrice Bellard 5 * Copyright (c) 2012,2013 Artyom Tarasenko 6 * Copyright (c) 2018 Mark Cave-Ayland 7 * 8 * Permission is hereby granted, free of charge, to any person obtaining a copy 9 * of this software and associated documentation files (the "Software"), to deal 10 * in the Software without restriction, including without limitation the rights 11 * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell 12 * copies of the Software, and to permit persons to whom the Software is 13 * furnished to do so, subject to the following conditions: 14 * 15 * The above copyright notice and this permission notice shall be included in 16 * all copies or substantial portions of the Software. 17 * 18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 19 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 20 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 21 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER 22 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, 23 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN 24 * THE SOFTWARE. 25 */ 26 27 #include "qemu/osdep.h" 28 #include "hw/pci/pci.h" 29 #include "hw/pci/pci_bridge.h" 30 #include "hw/pci/pci_bus.h" 31 #include "hw/pci-bridge/simba.h" 32 33 /* 34 * Chipset docs: 35 * APB: "Advanced PCI Bridge (APB) User's Manual", 36 * http://www.sun.com/processors/manuals/805-1251.pdf 37 */ 38 39 static void simba_pci_bridge_realize(PCIDevice *dev, Error **errp) 40 { 41 /* 42 * command register: 43 * According to PCI bridge spec, after reset 44 * bus master bit is off 45 * memory space enable bit is off 46 * According to manual (805-1251.pdf). 47 * the reset value should be zero unless the boot pin is tied high 48 * (which is true) and thus it should be PCI_COMMAND_MEMORY. 49 */ 50 SimbaPCIBridge *br = SIMBA_PCI_BRIDGE(dev); 51 52 pci_bridge_initfn(dev, TYPE_PCI_BUS); 53 54 pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); 55 pci_set_word(dev->config + PCI_STATUS, 56 PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | 57 PCI_STATUS_DEVSEL_MEDIUM); 58 59 /* Allow 32-bit IO addresses */ 60 pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); 61 pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); 62 pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); 63 pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); 64 65 pci_bridge_update_mappings(PCI_BRIDGE(br)); 66 } 67 68 static void simba_pci_bridge_class_init(ObjectClass *klass, void *data) 69 { 70 DeviceClass *dc = DEVICE_CLASS(klass); 71 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 72 73 k->realize = simba_pci_bridge_realize; 74 k->exit = pci_bridge_exitfn; 75 k->vendor_id = PCI_VENDOR_ID_SUN; 76 k->device_id = PCI_DEVICE_ID_SUN_SIMBA; 77 k->revision = 0x11; 78 k->config_write = pci_bridge_write_config; 79 k->is_bridge = true; 80 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 81 dc->reset = pci_bridge_reset; 82 dc->vmsd = &vmstate_pci_device; 83 } 84 85 static const TypeInfo simba_pci_bridge_info = { 86 .name = TYPE_SIMBA_PCI_BRIDGE, 87 .parent = TYPE_PCI_BRIDGE, 88 .class_init = simba_pci_bridge_class_init, 89 .instance_size = sizeof(SimbaPCIBridge), 90 .interfaces = (InterfaceInfo[]) { 91 { INTERFACE_CONVENTIONAL_PCI_DEVICE }, 92 { }, 93 }, 94 }; 95 96 static void simba_register_types(void) 97 { 98 type_register_static(&simba_pci_bridge_info); 99 } 100 101 type_init(simba_register_types) 102