1 /* 2 * Base class for PCI Express Root Ports 3 * 4 * Copyright (C) 2017 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel@redhat.com> 8 * 9 * Most of the code was migrated from hw/pci-bridge/ioh3420. 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qapi/error.h" 17 #include "hw/pci/pcie_port.h" 18 19 static void rp_aer_vector_update(PCIDevice *d) 20 { 21 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); 22 23 if (rpc->aer_vector) { 24 pcie_aer_root_set_vector(d, rpc->aer_vector(d)); 25 } 26 } 27 28 static void rp_write_config(PCIDevice *d, uint32_t address, 29 uint32_t val, int len) 30 { 31 uint32_t root_cmd = 32 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); 33 34 pci_bridge_write_config(d, address, val, len); 35 rp_aer_vector_update(d); 36 pcie_cap_slot_write_config(d, address, val, len); 37 pcie_aer_write_config(d, address, val, len); 38 pcie_aer_root_write_config(d, address, val, len, root_cmd); 39 } 40 41 static void rp_reset(DeviceState *qdev) 42 { 43 PCIDevice *d = PCI_DEVICE(qdev); 44 45 rp_aer_vector_update(d); 46 pcie_cap_root_reset(d); 47 pcie_cap_deverr_reset(d); 48 pcie_cap_slot_reset(d); 49 pcie_cap_arifwd_reset(d); 50 pcie_acs_reset(d); 51 pcie_aer_root_reset(d); 52 pci_bridge_reset(qdev); 53 pci_bridge_disable_base_limit(d); 54 } 55 56 static void rp_realize(PCIDevice *d, Error **errp) 57 { 58 PCIEPort *p = PCIE_PORT(d); 59 PCIESlot *s = PCIE_SLOT(d); 60 PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d); 61 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); 62 int rc; 63 64 pci_config_set_interrupt_pin(d->config, 1); 65 pci_bridge_initfn(d, TYPE_PCIE_BUS); 66 pcie_port_init_reg(d); 67 68 rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, 69 rpc->ssid, errp); 70 if (rc < 0) { 71 error_append_hint(errp, "Can't init SSV ID, error %d\n", rc); 72 goto err_bridge; 73 } 74 75 if (rpc->interrupts_init) { 76 rc = rpc->interrupts_init(d, errp); 77 if (rc < 0) { 78 goto err_bridge; 79 } 80 } 81 82 rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, 83 p->port, errp); 84 if (rc < 0) { 85 error_append_hint(errp, "Can't add Root Port capability, " 86 "error %d\n", rc); 87 goto err_int; 88 } 89 90 pcie_cap_arifwd_init(d); 91 pcie_cap_deverr_init(d); 92 pcie_cap_slot_init(d, s->slot); 93 pcie_cap_root_init(d); 94 95 pcie_chassis_create(s->chassis); 96 rc = pcie_chassis_add_slot(s); 97 if (rc < 0) { 98 error_setg(errp, "Can't add chassis slot, error %d", rc); 99 goto err_pcie_cap; 100 } 101 102 rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset, 103 PCI_ERR_SIZEOF, errp); 104 if (rc < 0) { 105 goto err; 106 } 107 pcie_aer_root_init(d); 108 rp_aer_vector_update(d); 109 110 if (rpc->acs_offset) { 111 pcie_acs_init(d, rpc->acs_offset); 112 } 113 return; 114 115 err: 116 pcie_chassis_del_slot(s); 117 err_pcie_cap: 118 pcie_cap_exit(d); 119 err_int: 120 if (rpc->interrupts_uninit) { 121 rpc->interrupts_uninit(d); 122 } 123 err_bridge: 124 pci_bridge_exitfn(d); 125 } 126 127 static void rp_exit(PCIDevice *d) 128 { 129 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); 130 PCIESlot *s = PCIE_SLOT(d); 131 132 pcie_aer_exit(d); 133 pcie_chassis_del_slot(s); 134 pcie_cap_exit(d); 135 if (rpc->interrupts_uninit) { 136 rpc->interrupts_uninit(d); 137 } 138 pci_bridge_exitfn(d); 139 } 140 141 static Property rp_props[] = { 142 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, 143 QEMU_PCIE_SLTCAP_PCP_BITNR, true), 144 DEFINE_PROP_END_OF_LIST() 145 }; 146 147 static void rp_instance_post_init(Object *obj) 148 { 149 PCIESlot *s = PCIE_SLOT(obj); 150 151 if (!s->speed) { 152 s->speed = QEMU_PCI_EXP_LNK_2_5GT; 153 } 154 155 if (!s->width) { 156 s->width = QEMU_PCI_EXP_LNK_X1; 157 } 158 } 159 160 static void rp_class_init(ObjectClass *klass, void *data) 161 { 162 DeviceClass *dc = DEVICE_CLASS(klass); 163 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 164 165 k->is_bridge = true; 166 k->config_write = rp_write_config; 167 k->realize = rp_realize; 168 k->exit = rp_exit; 169 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 170 dc->reset = rp_reset; 171 dc->props = rp_props; 172 } 173 174 static const TypeInfo rp_info = { 175 .name = TYPE_PCIE_ROOT_PORT, 176 .parent = TYPE_PCIE_SLOT, 177 .instance_post_init = rp_instance_post_init, 178 .class_init = rp_class_init, 179 .abstract = true, 180 .class_size = sizeof(PCIERootPortClass), 181 .interfaces = (InterfaceInfo[]) { 182 { INTERFACE_PCIE_DEVICE }, 183 { } 184 }, 185 }; 186 187 static void rp_register_types(void) 188 { 189 type_register_static(&rp_info); 190 } 191 192 type_init(rp_register_types) 193