1 /* 2 * Base class for PCI Express Root Ports 3 * 4 * Copyright (C) 2017 Red Hat Inc 5 * 6 * Authors: 7 * Marcel Apfelbaum <marcel@redhat.com> 8 * 9 * Most of the code was migrated from hw/pci-bridge/ioh3420. 10 * 11 * This work is licensed under the terms of the GNU GPL, version 2 or later. 12 * See the COPYING file in the top-level directory. 13 */ 14 15 #include "qemu/osdep.h" 16 #include "qapi/error.h" 17 #include "qemu/module.h" 18 #include "hw/pci/pcie_port.h" 19 20 static void rp_aer_vector_update(PCIDevice *d) 21 { 22 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); 23 24 if (rpc->aer_vector) { 25 pcie_aer_root_set_vector(d, rpc->aer_vector(d)); 26 } 27 } 28 29 static void rp_write_config(PCIDevice *d, uint32_t address, 30 uint32_t val, int len) 31 { 32 uint32_t root_cmd = 33 pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND); 34 uint16_t slt_ctl, slt_sta; 35 36 pcie_cap_slot_get(d, &slt_ctl, &slt_sta); 37 38 pci_bridge_write_config(d, address, val, len); 39 rp_aer_vector_update(d); 40 pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len); 41 pcie_aer_write_config(d, address, val, len); 42 pcie_aer_root_write_config(d, address, val, len, root_cmd); 43 } 44 45 static void rp_reset(DeviceState *qdev) 46 { 47 PCIDevice *d = PCI_DEVICE(qdev); 48 49 rp_aer_vector_update(d); 50 pcie_cap_root_reset(d); 51 pcie_cap_deverr_reset(d); 52 pcie_cap_slot_reset(d); 53 pcie_cap_arifwd_reset(d); 54 pcie_acs_reset(d); 55 pcie_aer_root_reset(d); 56 pci_bridge_reset(qdev); 57 pci_bridge_disable_base_limit(d); 58 } 59 60 static void rp_realize(PCIDevice *d, Error **errp) 61 { 62 PCIEPort *p = PCIE_PORT(d); 63 PCIESlot *s = PCIE_SLOT(d); 64 PCIDeviceClass *dc = PCI_DEVICE_GET_CLASS(d); 65 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); 66 int rc; 67 68 pci_config_set_interrupt_pin(d->config, 1); 69 pci_bridge_initfn(d, TYPE_PCIE_BUS); 70 pcie_port_init_reg(d); 71 72 rc = pci_bridge_ssvid_init(d, rpc->ssvid_offset, dc->vendor_id, 73 rpc->ssid, errp); 74 if (rc < 0) { 75 error_append_hint(errp, "Can't init SSV ID, error %d\n", rc); 76 goto err_bridge; 77 } 78 79 if (rpc->interrupts_init) { 80 rc = rpc->interrupts_init(d, errp); 81 if (rc < 0) { 82 goto err_bridge; 83 } 84 } 85 86 rc = pcie_cap_init(d, rpc->exp_offset, PCI_EXP_TYPE_ROOT_PORT, 87 p->port, errp); 88 if (rc < 0) { 89 error_append_hint(errp, "Can't add Root Port capability, " 90 "error %d\n", rc); 91 goto err_int; 92 } 93 94 pcie_cap_arifwd_init(d); 95 pcie_cap_deverr_init(d); 96 pcie_cap_slot_init(d, s->slot); 97 pcie_cap_root_init(d); 98 99 pcie_chassis_create(s->chassis); 100 rc = pcie_chassis_add_slot(s); 101 if (rc < 0) { 102 error_setg(errp, "Can't add chassis slot, error %d", rc); 103 goto err_pcie_cap; 104 } 105 106 rc = pcie_aer_init(d, PCI_ERR_VER, rpc->aer_offset, 107 PCI_ERR_SIZEOF, errp); 108 if (rc < 0) { 109 goto err; 110 } 111 pcie_aer_root_init(d); 112 rp_aer_vector_update(d); 113 114 if (rpc->acs_offset) { 115 pcie_acs_init(d, rpc->acs_offset); 116 } 117 return; 118 119 err: 120 pcie_chassis_del_slot(s); 121 err_pcie_cap: 122 pcie_cap_exit(d); 123 err_int: 124 if (rpc->interrupts_uninit) { 125 rpc->interrupts_uninit(d); 126 } 127 err_bridge: 128 pci_bridge_exitfn(d); 129 } 130 131 static void rp_exit(PCIDevice *d) 132 { 133 PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d); 134 PCIESlot *s = PCIE_SLOT(d); 135 136 pcie_aer_exit(d); 137 pcie_chassis_del_slot(s); 138 pcie_cap_exit(d); 139 if (rpc->interrupts_uninit) { 140 rpc->interrupts_uninit(d); 141 } 142 pci_bridge_exitfn(d); 143 } 144 145 static Property rp_props[] = { 146 DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, 147 QEMU_PCIE_SLTCAP_PCP_BITNR, true), 148 DEFINE_PROP_END_OF_LIST() 149 }; 150 151 static void rp_instance_post_init(Object *obj) 152 { 153 PCIESlot *s = PCIE_SLOT(obj); 154 155 if (!s->speed) { 156 s->speed = QEMU_PCI_EXP_LNK_2_5GT; 157 } 158 159 if (!s->width) { 160 s->width = QEMU_PCI_EXP_LNK_X1; 161 } 162 } 163 164 static void rp_class_init(ObjectClass *klass, void *data) 165 { 166 DeviceClass *dc = DEVICE_CLASS(klass); 167 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 168 169 k->is_bridge = true; 170 k->config_write = rp_write_config; 171 k->realize = rp_realize; 172 k->exit = rp_exit; 173 set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); 174 dc->reset = rp_reset; 175 dc->props = rp_props; 176 } 177 178 static const TypeInfo rp_info = { 179 .name = TYPE_PCIE_ROOT_PORT, 180 .parent = TYPE_PCIE_SLOT, 181 .instance_post_init = rp_instance_post_init, 182 .class_init = rp_class_init, 183 .abstract = true, 184 .class_size = sizeof(PCIERootPortClass), 185 .interfaces = (InterfaceInfo[]) { 186 { INTERFACE_PCIE_DEVICE }, 187 { } 188 }, 189 }; 190 191 static void rp_register_types(void) 192 { 193 type_register_static(&rp_info); 194 } 195 196 type_init(rp_register_types) 197