1 /*
2  * QEMU Generic PCIE-PCI Bridge
3  *
4  * Copyright (c) 2017 Aleksandr Bezzubikov
5  *
6  * This work is licensed under the terms of the GNU GPL, version 2 or later.
7  * See the COPYING file in the top-level directory.
8  */
9 
10 #include "qemu/osdep.h"
11 #include "qapi/error.h"
12 #include "hw/pci/pci.h"
13 #include "hw/pci/pci_bus.h"
14 #include "hw/pci/pci_bridge.h"
15 #include "hw/pci/msi.h"
16 #include "hw/pci/shpc.h"
17 #include "hw/pci/slotid_cap.h"
18 
19 typedef struct PCIEPCIBridge {
20     /*< private >*/
21     PCIBridge parent_obj;
22 
23     OnOffAuto msi;
24     MemoryRegion shpc_bar;
25     /*< public >*/
26 } PCIEPCIBridge;
27 
28 #define TYPE_PCIE_PCI_BRIDGE_DEV "pcie-pci-bridge"
29 #define PCIE_PCI_BRIDGE_DEV(obj) \
30         OBJECT_CHECK(PCIEPCIBridge, (obj), TYPE_PCIE_PCI_BRIDGE_DEV)
31 
32 static void pcie_pci_bridge_realize(PCIDevice *d, Error **errp)
33 {
34     PCIBridge *br = PCI_BRIDGE(d);
35     PCIEPCIBridge *pcie_br = PCIE_PCI_BRIDGE_DEV(d);
36     int rc, pos;
37 
38     pci_bridge_initfn(d, TYPE_PCI_BUS);
39 
40     d->config[PCI_INTERRUPT_PIN] = 0x1;
41     memory_region_init(&pcie_br->shpc_bar, OBJECT(d), "shpc-bar",
42                        shpc_bar_size(d));
43     rc = shpc_init(d, &br->sec_bus, &pcie_br->shpc_bar, 0, errp);
44     if (rc) {
45         goto error;
46     }
47 
48     rc = pcie_cap_init(d, 0, PCI_EXP_TYPE_PCI_BRIDGE, 0, errp);
49     if (rc < 0) {
50         goto cap_error;
51     }
52 
53     pos = pci_add_capability(d, PCI_CAP_ID_PM, 0, PCI_PM_SIZEOF, errp);
54     if (pos < 0) {
55         goto pm_error;
56     }
57     d->exp.pm_cap = pos;
58     pci_set_word(d->config + pos + PCI_PM_PMC, 0x3);
59 
60     pcie_cap_arifwd_init(d);
61     pcie_cap_deverr_init(d);
62 
63     rc = pcie_aer_init(d, PCI_ERR_VER, 0x100, PCI_ERR_SIZEOF, errp);
64     if (rc < 0) {
65         goto aer_error;
66     }
67 
68     if (pcie_br->msi != ON_OFF_AUTO_OFF) {
69         rc = msi_init(d, 0, 1, true, true, errp);
70         if (rc < 0) {
71             goto msi_error;
72         }
73     }
74     pci_register_bar(d, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
75                      PCI_BASE_ADDRESS_MEM_TYPE_64, &pcie_br->shpc_bar);
76     return;
77 
78 msi_error:
79     pcie_aer_exit(d);
80 aer_error:
81 pm_error:
82     pcie_cap_exit(d);
83 cap_error:
84     shpc_free(d);
85 error:
86     pci_bridge_exitfn(d);
87 }
88 
89 static void pcie_pci_bridge_exit(PCIDevice *d)
90 {
91     PCIEPCIBridge *bridge_dev = PCIE_PCI_BRIDGE_DEV(d);
92     pcie_cap_exit(d);
93     shpc_cleanup(d, &bridge_dev->shpc_bar);
94     pci_bridge_exitfn(d);
95 }
96 
97 static void pcie_pci_bridge_reset(DeviceState *qdev)
98 {
99     PCIDevice *d = PCI_DEVICE(qdev);
100     pci_bridge_reset(qdev);
101     msi_reset(d);
102     shpc_reset(d);
103 }
104 
105 static void pcie_pci_bridge_write_config(PCIDevice *d,
106         uint32_t address, uint32_t val, int len)
107 {
108     pci_bridge_write_config(d, address, val, len);
109     msi_write_config(d, address, val, len);
110     shpc_cap_write_config(d, address, val, len);
111 }
112 
113 static Property pcie_pci_bridge_dev_properties[] = {
114         DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_ON),
115         DEFINE_PROP_END_OF_LIST(),
116 };
117 
118 static const VMStateDescription pcie_pci_bridge_dev_vmstate = {
119         .name = TYPE_PCIE_PCI_BRIDGE_DEV,
120         .fields = (VMStateField[]) {
121             VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
122             SHPC_VMSTATE(shpc, PCIDevice, NULL),
123             VMSTATE_END_OF_LIST()
124         }
125 };
126 
127 static void pcie_pci_bridge_hotplug_cb(HotplugHandler *hotplug_dev,
128                                       DeviceState *dev, Error **errp)
129 {
130     PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
131 
132     if (!shpc_present(pci_hotplug_dev)) {
133         error_setg(errp, "standard hotplug controller has been disabled for "
134                    "this %s", TYPE_PCIE_PCI_BRIDGE_DEV);
135         return;
136     }
137     shpc_device_hotplug_cb(hotplug_dev, dev, errp);
138 }
139 
140 static void pcie_pci_bridge_hot_unplug_request_cb(HotplugHandler *hotplug_dev,
141                                                  DeviceState *dev,
142                                                  Error **errp)
143 {
144     PCIDevice *pci_hotplug_dev = PCI_DEVICE(hotplug_dev);
145 
146     if (!shpc_present(pci_hotplug_dev)) {
147         error_setg(errp, "standard hotplug controller has been disabled for "
148                    "this %s", TYPE_PCIE_PCI_BRIDGE_DEV);
149         return;
150     }
151     shpc_device_hot_unplug_request_cb(hotplug_dev, dev, errp);
152 }
153 
154 static void pcie_pci_bridge_class_init(ObjectClass *klass, void *data)
155 {
156     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
157     DeviceClass *dc = DEVICE_CLASS(klass);
158     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
159 
160     k->is_express = 1;
161     k->is_bridge = 1;
162     k->vendor_id = PCI_VENDOR_ID_REDHAT;
163     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_BRIDGE;
164     k->realize = pcie_pci_bridge_realize;
165     k->exit = pcie_pci_bridge_exit;
166     k->config_write = pcie_pci_bridge_write_config;
167     dc->vmsd = &pcie_pci_bridge_dev_vmstate;
168     dc->props = pcie_pci_bridge_dev_properties;
169     dc->vmsd = &pcie_pci_bridge_dev_vmstate;
170     dc->reset = &pcie_pci_bridge_reset;
171     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
172     hc->plug = pcie_pci_bridge_hotplug_cb;
173     hc->unplug_request = pcie_pci_bridge_hot_unplug_request_cb;
174 }
175 
176 static const TypeInfo pcie_pci_bridge_info = {
177         .name = TYPE_PCIE_PCI_BRIDGE_DEV,
178         .parent = TYPE_PCI_BRIDGE,
179         .instance_size = sizeof(PCIEPCIBridge),
180         .class_init = pcie_pci_bridge_class_init,
181         .interfaces = (InterfaceInfo[]) {
182             { TYPE_HOTPLUG_HANDLER },
183             { },
184         }
185 };
186 
187 static void pciepci_register(void)
188 {
189     type_register_static(&pcie_pci_bridge_info);
190 }
191 
192 type_init(pciepci_register);
193