xref: /openbmc/qemu/hw/pci-bridge/pci_bridge_dev.c (revision 88c1ee73)
1 /*
2  * Standard PCI Bridge Device
3  *
4  * Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <mst@redhat.com>
5  *
6  * http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #include "hw/pci/pci_bridge.h"
23 #include "hw/pci/pci_ids.h"
24 #include "hw/pci/msi.h"
25 #include "hw/pci/shpc.h"
26 #include "hw/pci/slotid_cap.h"
27 #include "exec/memory.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/hotplug.h"
30 
31 #define TYPE_PCI_BRIDGE_DEV "pci-bridge"
32 #define PCI_BRIDGE_DEV(obj) \
33     OBJECT_CHECK(PCIBridgeDev, (obj), TYPE_PCI_BRIDGE_DEV)
34 
35 struct PCIBridgeDev {
36     /*< private >*/
37     PCIBridge parent_obj;
38     /*< public >*/
39 
40     MemoryRegion bar;
41     uint8_t chassis_nr;
42 #define PCI_BRIDGE_DEV_F_MSI_REQ 0
43     uint32_t flags;
44 };
45 typedef struct PCIBridgeDev PCIBridgeDev;
46 
47 static int pci_bridge_dev_initfn(PCIDevice *dev)
48 {
49     PCIBridge *br = PCI_BRIDGE(dev);
50     PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
51     int err;
52 
53     err = pci_bridge_initfn(dev, TYPE_PCI_BUS);
54     if (err) {
55         goto bridge_error;
56     }
57     dev->config[PCI_INTERRUPT_PIN] = 0x1;
58     memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev));
59     err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
60     if (err) {
61         goto shpc_error;
62     }
63     err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0);
64     if (err) {
65         goto slotid_error;
66     }
67     if ((bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_MSI_REQ)) &&
68         msi_supported) {
69         err = msi_init(dev, 0, 1, true, true);
70         if (err < 0) {
71             goto msi_error;
72         }
73     }
74     /* TODO: spec recommends using 64 bit prefetcheable BAR.
75      * Check whether that works well. */
76     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
77 		     PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
78     return 0;
79 msi_error:
80     slotid_cap_cleanup(dev);
81 slotid_error:
82     shpc_cleanup(dev, &bridge_dev->bar);
83 shpc_error:
84     memory_region_destroy(&bridge_dev->bar);
85     pci_bridge_exitfn(dev);
86 bridge_error:
87     return err;
88 }
89 
90 static void pci_bridge_dev_exitfn(PCIDevice *dev)
91 {
92     PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
93     if (msi_present(dev)) {
94         msi_uninit(dev);
95     }
96     slotid_cap_cleanup(dev);
97     shpc_cleanup(dev, &bridge_dev->bar);
98     memory_region_destroy(&bridge_dev->bar);
99     pci_bridge_exitfn(dev);
100 }
101 
102 static void pci_bridge_dev_write_config(PCIDevice *d,
103                                         uint32_t address, uint32_t val, int len)
104 {
105     pci_bridge_write_config(d, address, val, len);
106     if (msi_present(d)) {
107         msi_write_config(d, address, val, len);
108     }
109     shpc_cap_write_config(d, address, val, len);
110 }
111 
112 static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
113 {
114     PCIDevice *dev = PCI_DEVICE(qdev);
115 
116     pci_bridge_reset(qdev);
117     shpc_reset(dev);
118 }
119 
120 static Property pci_bridge_dev_properties[] = {
121                     /* Note: 0 is not a legal chassis number. */
122     DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0),
123     DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true),
124     DEFINE_PROP_END_OF_LIST(),
125 };
126 
127 static const VMStateDescription pci_bridge_dev_vmstate = {
128     .name = "pci_bridge",
129     .fields = (VMStateField[]) {
130         VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
131         SHPC_VMSTATE(shpc, PCIDevice),
132         VMSTATE_END_OF_LIST()
133     }
134 };
135 
136 static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
137 {
138     DeviceClass *dc = DEVICE_CLASS(klass);
139     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
140     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
141 
142     k->init = pci_bridge_dev_initfn;
143     k->exit = pci_bridge_dev_exitfn;
144     k->config_write = pci_bridge_dev_write_config;
145     k->vendor_id = PCI_VENDOR_ID_REDHAT;
146     k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE;
147     k->class_id = PCI_CLASS_BRIDGE_PCI;
148     k->is_bridge = 1,
149     dc->desc = "Standard PCI Bridge";
150     dc->reset = qdev_pci_bridge_dev_reset;
151     dc->props = pci_bridge_dev_properties;
152     dc->vmsd = &pci_bridge_dev_vmstate;
153     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
154     hc->plug = shpc_device_hotplug_cb;
155     hc->unplug = shpc_device_hot_unplug_cb;
156 }
157 
158 static const TypeInfo pci_bridge_dev_info = {
159     .name          = TYPE_PCI_BRIDGE_DEV,
160     .parent        = TYPE_PCI_BRIDGE,
161     .instance_size = sizeof(PCIBridgeDev),
162     .class_init = pci_bridge_dev_class_init,
163     .interfaces = (InterfaceInfo[]) {
164         { TYPE_HOTPLUG_HANDLER },
165         { }
166     }
167 };
168 
169 static void pci_bridge_dev_register(void)
170 {
171     type_register_static(&pci_bridge_dev_info);
172 }
173 
174 type_init(pci_bridge_dev_register);
175