xref: /openbmc/qemu/hw/pci-bridge/pci_bridge_dev.c (revision 77a8257e)
1 /*
2  * Standard PCI Bridge Device
3  *
4  * Copyright (c) 2011 Red Hat Inc. Author: Michael S. Tsirkin <mst@redhat.com>
5  *
6  * http://www.pcisig.com/specifications/conventional/pci_to_pci_bridge_architecture/
7  *
8  * This program is free software; you can redistribute it and/or modify
9  * it under the terms of the GNU General Public License as published by
10  * the Free Software Foundation; either version 2 of the License, or
11  * (at your option) any later version.
12  *
13  * This program is distributed in the hope that it will be useful,
14  * but WITHOUT ANY WARRANTY; without even the implied warranty of
15  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
16  * GNU General Public License for more details.
17  *
18  * You should have received a copy of the GNU General Public License along
19  * with this program; if not, see <http://www.gnu.org/licenses/>.
20  */
21 
22 #include "hw/pci/pci_bridge.h"
23 #include "hw/pci/pci_ids.h"
24 #include "hw/pci/msi.h"
25 #include "hw/pci/shpc.h"
26 #include "hw/pci/slotid_cap.h"
27 #include "exec/memory.h"
28 #include "hw/pci/pci_bus.h"
29 #include "hw/hotplug.h"
30 
31 #define TYPE_PCI_BRIDGE_DEV "pci-bridge"
32 #define PCI_BRIDGE_DEV(obj) \
33     OBJECT_CHECK(PCIBridgeDev, (obj), TYPE_PCI_BRIDGE_DEV)
34 
35 struct PCIBridgeDev {
36     /*< private >*/
37     PCIBridge parent_obj;
38     /*< public >*/
39 
40     MemoryRegion bar;
41     uint8_t chassis_nr;
42 #define PCI_BRIDGE_DEV_F_MSI_REQ 0
43     uint32_t flags;
44 };
45 typedef struct PCIBridgeDev PCIBridgeDev;
46 
47 static int pci_bridge_dev_initfn(PCIDevice *dev)
48 {
49     PCIBridge *br = PCI_BRIDGE(dev);
50     PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
51     int err;
52 
53     err = pci_bridge_initfn(dev, TYPE_PCI_BUS);
54     if (err) {
55         goto bridge_error;
56     }
57     dev->config[PCI_INTERRUPT_PIN] = 0x1;
58     memory_region_init(&bridge_dev->bar, OBJECT(dev), "shpc-bar", shpc_bar_size(dev));
59     err = shpc_init(dev, &br->sec_bus, &bridge_dev->bar, 0);
60     if (err) {
61         goto shpc_error;
62     }
63     err = slotid_cap_init(dev, 0, bridge_dev->chassis_nr, 0);
64     if (err) {
65         goto slotid_error;
66     }
67     if ((bridge_dev->flags & (1 << PCI_BRIDGE_DEV_F_MSI_REQ)) &&
68         msi_supported) {
69         err = msi_init(dev, 0, 1, true, true);
70         if (err < 0) {
71             goto msi_error;
72         }
73     }
74     /* TODO: spec recommends using 64 bit prefetcheable BAR.
75      * Check whether that works well. */
76     pci_register_bar(dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY |
77 		     PCI_BASE_ADDRESS_MEM_TYPE_64, &bridge_dev->bar);
78     return 0;
79 msi_error:
80     slotid_cap_cleanup(dev);
81 slotid_error:
82     shpc_cleanup(dev, &bridge_dev->bar);
83 shpc_error:
84     pci_bridge_exitfn(dev);
85 bridge_error:
86     return err;
87 }
88 
89 static void pci_bridge_dev_exitfn(PCIDevice *dev)
90 {
91     PCIBridgeDev *bridge_dev = PCI_BRIDGE_DEV(dev);
92     if (msi_present(dev)) {
93         msi_uninit(dev);
94     }
95     slotid_cap_cleanup(dev);
96     shpc_cleanup(dev, &bridge_dev->bar);
97     pci_bridge_exitfn(dev);
98 }
99 
100 static void pci_bridge_dev_instance_finalize(Object *obj)
101 {
102     shpc_free(PCI_DEVICE(obj));
103 }
104 
105 static void pci_bridge_dev_write_config(PCIDevice *d,
106                                         uint32_t address, uint32_t val, int len)
107 {
108     pci_bridge_write_config(d, address, val, len);
109     if (msi_present(d)) {
110         msi_write_config(d, address, val, len);
111     }
112     shpc_cap_write_config(d, address, val, len);
113 }
114 
115 static void qdev_pci_bridge_dev_reset(DeviceState *qdev)
116 {
117     PCIDevice *dev = PCI_DEVICE(qdev);
118 
119     pci_bridge_reset(qdev);
120     shpc_reset(dev);
121 }
122 
123 static Property pci_bridge_dev_properties[] = {
124                     /* Note: 0 is not a legal chassis number. */
125     DEFINE_PROP_UINT8("chassis_nr", PCIBridgeDev, chassis_nr, 0),
126     DEFINE_PROP_BIT("msi", PCIBridgeDev, flags, PCI_BRIDGE_DEV_F_MSI_REQ, true),
127     DEFINE_PROP_END_OF_LIST(),
128 };
129 
130 static const VMStateDescription pci_bridge_dev_vmstate = {
131     .name = "pci_bridge",
132     .fields = (VMStateField[]) {
133         VMSTATE_PCI_DEVICE(parent_obj, PCIBridge),
134         SHPC_VMSTATE(shpc, PCIDevice),
135         VMSTATE_END_OF_LIST()
136     }
137 };
138 
139 static void pci_bridge_dev_class_init(ObjectClass *klass, void *data)
140 {
141     DeviceClass *dc = DEVICE_CLASS(klass);
142     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
143     HotplugHandlerClass *hc = HOTPLUG_HANDLER_CLASS(klass);
144 
145     k->init = pci_bridge_dev_initfn;
146     k->exit = pci_bridge_dev_exitfn;
147     k->config_write = pci_bridge_dev_write_config;
148     k->vendor_id = PCI_VENDOR_ID_REDHAT;
149     k->device_id = PCI_DEVICE_ID_REDHAT_BRIDGE;
150     k->class_id = PCI_CLASS_BRIDGE_PCI;
151     k->is_bridge = 1,
152     dc->desc = "Standard PCI Bridge";
153     dc->reset = qdev_pci_bridge_dev_reset;
154     dc->props = pci_bridge_dev_properties;
155     dc->vmsd = &pci_bridge_dev_vmstate;
156     set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories);
157     hc->plug = shpc_device_hotplug_cb;
158     hc->unplug_request = shpc_device_hot_unplug_request_cb;
159 }
160 
161 static const TypeInfo pci_bridge_dev_info = {
162     .name              = TYPE_PCI_BRIDGE_DEV,
163     .parent            = TYPE_PCI_BRIDGE,
164     .instance_size     = sizeof(PCIBridgeDev),
165     .class_init        = pci_bridge_dev_class_init,
166     .instance_finalize = pci_bridge_dev_instance_finalize,
167     .interfaces = (InterfaceInfo[]) {
168         { TYPE_HOTPLUG_HANDLER },
169         { }
170     }
171 };
172 
173 static void pci_bridge_dev_register(void)
174 {
175     type_register_static(&pci_bridge_dev_info);
176 }
177 
178 type_init(pci_bridge_dev_register);
179