1 /* 2 * ioh3420.c 3 * Intel X58 north bridge IOH 4 * PCI Express root port device id 3420 5 * 6 * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp> 7 * VA Linux Systems Japan K.K. 8 * 9 * This program is free software; you can redistribute it and/or modify 10 * it under the terms of the GNU General Public License as published by 11 * the Free Software Foundation; either version 2 of the License, or 12 * (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License along 20 * with this program; if not, see <http://www.gnu.org/licenses/>. 21 */ 22 23 #include "qemu/osdep.h" 24 #include "hw/pci/pci_ids.h" 25 #include "hw/pci/msi.h" 26 #include "hw/pci/pcie.h" 27 #include "ioh3420.h" 28 29 #define PCI_DEVICE_ID_IOH_EPORT 0x3420 /* D0:F0 express mode */ 30 #define PCI_DEVICE_ID_IOH_REV 0x2 31 #define IOH_EP_SSVID_OFFSET 0x40 32 #define IOH_EP_SSVID_SVID PCI_VENDOR_ID_INTEL 33 #define IOH_EP_SSVID_SSID 0 34 #define IOH_EP_MSI_OFFSET 0x60 35 #define IOH_EP_MSI_SUPPORTED_FLAGS PCI_MSI_FLAGS_MASKBIT 36 #define IOH_EP_MSI_NR_VECTOR 2 37 #define IOH_EP_EXP_OFFSET 0x90 38 #define IOH_EP_AER_OFFSET 0x100 39 40 /* 41 * If two MSI vector are allocated, Advanced Error Interrupt Message Number 42 * is 1. otherwise 0. 43 * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number. 44 */ 45 static uint8_t ioh3420_aer_vector(const PCIDevice *d) 46 { 47 switch (msi_nr_vectors_allocated(d)) { 48 case 1: 49 return 0; 50 case 2: 51 return 1; 52 case 4: 53 case 8: 54 case 16: 55 case 32: 56 default: 57 break; 58 } 59 abort(); 60 return 0; 61 } 62 63 static int ioh3420_interrupts_init(PCIDevice *d, Error **errp) 64 { 65 int rc; 66 67 rc = msi_init(d, IOH_EP_MSI_OFFSET, IOH_EP_MSI_NR_VECTOR, 68 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_64BIT, 69 IOH_EP_MSI_SUPPORTED_FLAGS & PCI_MSI_FLAGS_MASKBIT, 70 errp); 71 if (rc < 0) { 72 assert(rc == -ENOTSUP); 73 } 74 75 return rc; 76 } 77 78 static void ioh3420_interrupts_uninit(PCIDevice *d) 79 { 80 msi_uninit(d); 81 } 82 83 static const VMStateDescription vmstate_ioh3420 = { 84 .name = "ioh-3240-express-root-port", 85 .version_id = 1, 86 .minimum_version_id = 1, 87 .post_load = pcie_cap_slot_post_load, 88 .fields = (VMStateField[]) { 89 VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot), 90 VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log, 91 PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog), 92 VMSTATE_END_OF_LIST() 93 } 94 }; 95 96 static void ioh3420_class_init(ObjectClass *klass, void *data) 97 { 98 DeviceClass *dc = DEVICE_CLASS(klass); 99 PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); 100 PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass); 101 102 k->vendor_id = PCI_VENDOR_ID_INTEL; 103 k->device_id = PCI_DEVICE_ID_IOH_EPORT; 104 k->revision = PCI_DEVICE_ID_IOH_REV; 105 dc->desc = "Intel IOH device id 3420 PCIE Root Port"; 106 dc->vmsd = &vmstate_ioh3420; 107 rpc->aer_vector = ioh3420_aer_vector; 108 rpc->interrupts_init = ioh3420_interrupts_init; 109 rpc->interrupts_uninit = ioh3420_interrupts_uninit; 110 rpc->exp_offset = IOH_EP_EXP_OFFSET; 111 rpc->aer_offset = IOH_EP_AER_OFFSET; 112 rpc->ssvid_offset = IOH_EP_SSVID_OFFSET; 113 rpc->ssid = IOH_EP_SSVID_SSID; 114 } 115 116 static const TypeInfo ioh3420_info = { 117 .name = "ioh3420", 118 .parent = TYPE_PCIE_ROOT_PORT, 119 .class_init = ioh3420_class_init, 120 }; 121 122 static void ioh3420_register_types(void) 123 { 124 type_register_static(&ioh3420_info); 125 } 126 127 type_init(ioh3420_register_types) 128