1 /*
2  * Generic PCI Express Root Port emulation
3  *
4  * Copyright (C) 2017 Red Hat Inc
5  *
6  * Authors:
7  *   Marcel Apfelbaum <marcel@redhat.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "hw/pci/msix.h"
16 #include "hw/pci/pcie_port.h"
17 
18 #define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
19 #define GEN_PCIE_ROOT_PORT(obj) \
20         OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT)
21 
22 #define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
23 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
24 
25 typedef struct GenPCIERootPort {
26     /*< private >*/
27     PCIESlot parent_obj;
28     /*< public >*/
29 
30     bool migrate_msix;
31 
32     /* additional resources to reserve on firmware init */
33     uint32_t bus_reserve;
34     uint64_t io_reserve;
35     uint64_t mem_reserve;
36     uint64_t pref32_reserve;
37     uint64_t pref64_reserve;
38 } GenPCIERootPort;
39 
40 static uint8_t gen_rp_aer_vector(const PCIDevice *d)
41 {
42     return 0;
43 }
44 
45 static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
46 {
47     int rc;
48 
49     rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
50 
51     if (rc < 0) {
52         assert(rc == -ENOTSUP);
53     } else {
54         msix_vector_use(d, 0);
55     }
56 
57     return rc;
58 }
59 
60 static void gen_rp_interrupts_uninit(PCIDevice *d)
61 {
62     msix_uninit_exclusive_bar(d);
63 }
64 
65 static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
66 {
67     GenPCIERootPort *rp = opaque;
68 
69     return rp->migrate_msix;
70 }
71 
72 static void gen_rp_realize(DeviceState *dev, Error **errp)
73 {
74     PCIDevice *d = PCI_DEVICE(dev);
75     GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
76     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
77 
78     rpc->parent_realize(dev, errp);
79 
80     int rc = pci_bridge_qemu_reserve_cap_init(d, 0, grp->bus_reserve,
81             grp->io_reserve, grp->mem_reserve, grp->pref32_reserve,
82             grp->pref64_reserve, errp);
83 
84     if (rc < 0) {
85         rpc->parent_class.exit(d);
86         return;
87     }
88 }
89 
90 static const VMStateDescription vmstate_rp_dev = {
91     .name = "pcie-root-port",
92     .version_id = 1,
93     .minimum_version_id = 1,
94     .post_load = pcie_cap_slot_post_load,
95     .fields = (VMStateField[]) {
96         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
97         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
98                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
99         VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
100                           GenPCIERootPort,
101                           gen_rp_test_migrate_msix),
102         VMSTATE_END_OF_LIST()
103     }
104 };
105 
106 static Property gen_rp_props[] = {
107     DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort, migrate_msix, true),
108     DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort, bus_reserve, -1),
109     DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort, io_reserve, -1),
110     DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort, mem_reserve, -1),
111     DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort, pref32_reserve, -1),
112     DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort, pref64_reserve, -1),
113     DEFINE_PROP_END_OF_LIST()
114 };
115 
116 static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
117 {
118     DeviceClass *dc = DEVICE_CLASS(klass);
119     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
120     PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
121 
122     k->vendor_id = PCI_VENDOR_ID_REDHAT;
123     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
124     dc->desc = "PCI Express Root Port";
125     dc->vmsd = &vmstate_rp_dev;
126     dc->props = gen_rp_props;
127 
128     rpc->parent_realize = dc->realize;
129     dc->realize = gen_rp_realize;
130 
131     rpc->aer_vector = gen_rp_aer_vector;
132     rpc->interrupts_init = gen_rp_interrupts_init;
133     rpc->interrupts_uninit = gen_rp_interrupts_uninit;
134     rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
135 }
136 
137 static const TypeInfo gen_rp_dev_info = {
138     .name          = TYPE_GEN_PCIE_ROOT_PORT,
139     .parent        = TYPE_PCIE_ROOT_PORT,
140     .instance_size = sizeof(GenPCIERootPort),
141     .class_init    = gen_rp_dev_class_init,
142 };
143 
144  static void gen_rp_register_types(void)
145  {
146     type_register_static(&gen_rp_dev_info);
147  }
148  type_init(gen_rp_register_types)
149