1 /*
2  * Generic PCI Express Root Port emulation
3  *
4  * Copyright (C) 2017 Red Hat Inc
5  *
6  * Authors:
7  *   Marcel Apfelbaum <marcel@redhat.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "hw/pci/msix.h"
17 #include "hw/pci/pcie_port.h"
18 
19 #define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
20 #define GEN_PCIE_ROOT_PORT(obj) \
21         OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT)
22 
23 #define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
24 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
25         (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
26 
27 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
28 
29 typedef struct GenPCIERootPort {
30     /*< private >*/
31     PCIESlot parent_obj;
32     /*< public >*/
33 
34     bool migrate_msix;
35 
36     /* additional resources to reserve */
37     PCIResReserve res_reserve;
38 } GenPCIERootPort;
39 
40 static uint8_t gen_rp_aer_vector(const PCIDevice *d)
41 {
42     return 0;
43 }
44 
45 static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
46 {
47     int rc;
48 
49     rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
50 
51     if (rc < 0) {
52         assert(rc == -ENOTSUP);
53     } else {
54         msix_vector_use(d, 0);
55     }
56 
57     return rc;
58 }
59 
60 static void gen_rp_interrupts_uninit(PCIDevice *d)
61 {
62     msix_uninit_exclusive_bar(d);
63 }
64 
65 static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
66 {
67     GenPCIERootPort *rp = opaque;
68 
69     return rp->migrate_msix;
70 }
71 
72 static void gen_rp_realize(DeviceState *dev, Error **errp)
73 {
74     PCIDevice *d = PCI_DEVICE(dev);
75     GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
76     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
77     Error *local_err = NULL;
78 
79     rpc->parent_realize(dev, &local_err);
80     if (local_err) {
81         error_propagate(errp, local_err);
82         return;
83     }
84 
85     int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
86                                               grp->res_reserve, errp);
87 
88     if (rc < 0) {
89         rpc->parent_class.exit(d);
90         return;
91     }
92 
93     if (!grp->res_reserve.io) {
94         pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
95                                      PCI_COMMAND_IO);
96         d->wmask[PCI_IO_BASE] = 0;
97         d->wmask[PCI_IO_LIMIT] = 0;
98     }
99 }
100 
101 static const VMStateDescription vmstate_rp_dev = {
102     .name = "pcie-root-port",
103     .priority = MIG_PRI_PCI_BUS,
104     .version_id = 1,
105     .minimum_version_id = 1,
106     .post_load = pcie_cap_slot_post_load,
107     .fields = (VMStateField[]) {
108         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
109         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
110                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
111         VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
112                           GenPCIERootPort,
113                           gen_rp_test_migrate_msix),
114         VMSTATE_END_OF_LIST()
115     }
116 };
117 
118 static Property gen_rp_props[] = {
119     DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
120                      migrate_msix, true),
121     DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
122                        res_reserve.bus, -1),
123     DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
124                      res_reserve.io, -1),
125     DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
126                      res_reserve.mem_non_pref, -1),
127     DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
128                      res_reserve.mem_pref_32, -1),
129     DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
130                      res_reserve.mem_pref_64, -1),
131     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
132                                 speed, PCIE_LINK_SPEED_16),
133     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
134                                 width, PCIE_LINK_WIDTH_32),
135     DEFINE_PROP_END_OF_LIST()
136 };
137 
138 static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
139 {
140     DeviceClass *dc = DEVICE_CLASS(klass);
141     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
142     PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
143 
144     k->vendor_id = PCI_VENDOR_ID_REDHAT;
145     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
146     dc->desc = "PCI Express Root Port";
147     dc->vmsd = &vmstate_rp_dev;
148     dc->props = gen_rp_props;
149 
150     device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
151 
152     rpc->aer_vector = gen_rp_aer_vector;
153     rpc->interrupts_init = gen_rp_interrupts_init;
154     rpc->interrupts_uninit = gen_rp_interrupts_uninit;
155     rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
156     rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
157 }
158 
159 static const TypeInfo gen_rp_dev_info = {
160     .name          = TYPE_GEN_PCIE_ROOT_PORT,
161     .parent        = TYPE_PCIE_ROOT_PORT,
162     .instance_size = sizeof(GenPCIERootPort),
163     .class_init    = gen_rp_dev_class_init,
164 };
165 
166  static void gen_rp_register_types(void)
167  {
168     type_register_static(&gen_rp_dev_info);
169  }
170  type_init(gen_rp_register_types)
171