1 /*
2  * Generic PCI Express Root Port emulation
3  *
4  * Copyright (C) 2017 Red Hat Inc
5  *
6  * Authors:
7  *   Marcel Apfelbaum <marcel@redhat.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "hw/pci/msix.h"
17 #include "hw/pci/pcie_port.h"
18 #include "migration/vmstate.h"
19 
20 #define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
21 #define GEN_PCIE_ROOT_PORT(obj) \
22         OBJECT_CHECK(GenPCIERootPort, (obj), TYPE_GEN_PCIE_ROOT_PORT)
23 
24 #define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
25 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
26         (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
27 
28 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
29 
30 typedef struct GenPCIERootPort {
31     /*< private >*/
32     PCIESlot parent_obj;
33     /*< public >*/
34 
35     bool migrate_msix;
36 
37     /* additional resources to reserve */
38     PCIResReserve res_reserve;
39 } GenPCIERootPort;
40 
41 static uint8_t gen_rp_aer_vector(const PCIDevice *d)
42 {
43     return 0;
44 }
45 
46 static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
47 {
48     int rc;
49 
50     rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
51 
52     if (rc < 0) {
53         assert(rc == -ENOTSUP);
54     } else {
55         msix_vector_use(d, 0);
56     }
57 
58     return rc;
59 }
60 
61 static void gen_rp_interrupts_uninit(PCIDevice *d)
62 {
63     msix_uninit_exclusive_bar(d);
64 }
65 
66 static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
67 {
68     GenPCIERootPort *rp = opaque;
69 
70     return rp->migrate_msix;
71 }
72 
73 static void gen_rp_realize(DeviceState *dev, Error **errp)
74 {
75     PCIDevice *d = PCI_DEVICE(dev);
76     GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
77     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
78     Error *local_err = NULL;
79 
80     rpc->parent_realize(dev, &local_err);
81     if (local_err) {
82         error_propagate(errp, local_err);
83         return;
84     }
85 
86     int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
87                                               grp->res_reserve, errp);
88 
89     if (rc < 0) {
90         rpc->parent_class.exit(d);
91         return;
92     }
93 
94     if (!grp->res_reserve.io) {
95         pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
96                                      PCI_COMMAND_IO);
97         d->wmask[PCI_IO_BASE] = 0;
98         d->wmask[PCI_IO_LIMIT] = 0;
99     }
100 }
101 
102 static const VMStateDescription vmstate_rp_dev = {
103     .name = "pcie-root-port",
104     .priority = MIG_PRI_PCI_BUS,
105     .version_id = 1,
106     .minimum_version_id = 1,
107     .post_load = pcie_cap_slot_post_load,
108     .fields = (VMStateField[]) {
109         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
110         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
111                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
112         VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
113                           GenPCIERootPort,
114                           gen_rp_test_migrate_msix),
115         VMSTATE_END_OF_LIST()
116     }
117 };
118 
119 static Property gen_rp_props[] = {
120     DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
121                      migrate_msix, true),
122     DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
123                        res_reserve.bus, -1),
124     DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
125                      res_reserve.io, -1),
126     DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
127                      res_reserve.mem_non_pref, -1),
128     DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
129                      res_reserve.mem_pref_32, -1),
130     DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
131                      res_reserve.mem_pref_64, -1),
132     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
133                                 speed, PCIE_LINK_SPEED_16),
134     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
135                                 width, PCIE_LINK_WIDTH_32),
136     DEFINE_PROP_END_OF_LIST()
137 };
138 
139 static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
140 {
141     DeviceClass *dc = DEVICE_CLASS(klass);
142     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
143     PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
144 
145     k->vendor_id = PCI_VENDOR_ID_REDHAT;
146     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
147     dc->desc = "PCI Express Root Port";
148     dc->vmsd = &vmstate_rp_dev;
149     dc->props = gen_rp_props;
150 
151     device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
152 
153     rpc->aer_vector = gen_rp_aer_vector;
154     rpc->interrupts_init = gen_rp_interrupts_init;
155     rpc->interrupts_uninit = gen_rp_interrupts_uninit;
156     rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
157     rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
158 }
159 
160 static const TypeInfo gen_rp_dev_info = {
161     .name          = TYPE_GEN_PCIE_ROOT_PORT,
162     .parent        = TYPE_PCIE_ROOT_PORT,
163     .instance_size = sizeof(GenPCIERootPort),
164     .class_init    = gen_rp_dev_class_init,
165 };
166 
167  static void gen_rp_register_types(void)
168  {
169     type_register_static(&gen_rp_dev_info);
170  }
171  type_init(gen_rp_register_types)
172