1 /*
2  * Generic PCI Express Root Port emulation
3  *
4  * Copyright (C) 2017 Red Hat Inc
5  *
6  * Authors:
7  *   Marcel Apfelbaum <marcel@redhat.com>
8  *
9  * This work is licensed under the terms of the GNU GPL, version 2 or later.
10  * See the COPYING file in the top-level directory.
11  */
12 
13 #include "qemu/osdep.h"
14 #include "qapi/error.h"
15 #include "qemu/module.h"
16 #include "hw/pci/msix.h"
17 #include "hw/pci/pcie_port.h"
18 #include "hw/qdev-properties.h"
19 #include "migration/vmstate.h"
20 #include "qom/object.h"
21 
22 #define TYPE_GEN_PCIE_ROOT_PORT                "pcie-root-port"
23 typedef struct GenPCIERootPort GenPCIERootPort;
24 DECLARE_INSTANCE_CHECKER(GenPCIERootPort, GEN_PCIE_ROOT_PORT,
25                          TYPE_GEN_PCIE_ROOT_PORT)
26 
27 #define GEN_PCIE_ROOT_PORT_AER_OFFSET           0x100
28 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
29         (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
30 
31 #define GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR       1
32 
33 struct GenPCIERootPort {
34     /*< private >*/
35     PCIESlot parent_obj;
36     /*< public >*/
37 
38     bool migrate_msix;
39 
40     /* additional resources to reserve */
41     PCIResReserve res_reserve;
42 };
43 
44 static uint8_t gen_rp_aer_vector(const PCIDevice *d)
45 {
46     return 0;
47 }
48 
49 static int gen_rp_interrupts_init(PCIDevice *d, Error **errp)
50 {
51     int rc;
52 
53     rc = msix_init_exclusive_bar(d, GEN_PCIE_ROOT_PORT_MSIX_NR_VECTOR, 0, errp);
54 
55     if (rc < 0) {
56         assert(rc == -ENOTSUP);
57     } else {
58         msix_vector_use(d, 0);
59     }
60 
61     return rc;
62 }
63 
64 static void gen_rp_interrupts_uninit(PCIDevice *d)
65 {
66     msix_uninit_exclusive_bar(d);
67 }
68 
69 static bool gen_rp_test_migrate_msix(void *opaque, int version_id)
70 {
71     GenPCIERootPort *rp = opaque;
72 
73     return rp->migrate_msix;
74 }
75 
76 static void gen_rp_realize(DeviceState *dev, Error **errp)
77 {
78     PCIDevice *d = PCI_DEVICE(dev);
79     GenPCIERootPort *grp = GEN_PCIE_ROOT_PORT(d);
80     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(d);
81     Error *local_err = NULL;
82 
83     rpc->parent_realize(dev, &local_err);
84     if (local_err) {
85         error_propagate(errp, local_err);
86         return;
87     }
88 
89     int rc = pci_bridge_qemu_reserve_cap_init(d, 0,
90                                               grp->res_reserve, errp);
91 
92     if (rc < 0) {
93         rpc->parent_class.exit(d);
94         return;
95     }
96 
97     if (!grp->res_reserve.io) {
98         pci_word_test_and_clear_mask(d->wmask + PCI_COMMAND,
99                                      PCI_COMMAND_IO);
100         d->wmask[PCI_IO_BASE] = 0;
101         d->wmask[PCI_IO_LIMIT] = 0;
102     }
103 }
104 
105 static const VMStateDescription vmstate_rp_dev = {
106     .name = "pcie-root-port",
107     .priority = MIG_PRI_PCI_BUS,
108     .version_id = 1,
109     .minimum_version_id = 1,
110     .post_load = pcie_cap_slot_post_load,
111     .fields = (VMStateField[]) {
112         VMSTATE_PCI_DEVICE(parent_obj.parent_obj.parent_obj, PCIESlot),
113         VMSTATE_STRUCT(parent_obj.parent_obj.parent_obj.exp.aer_log,
114                        PCIESlot, 0, vmstate_pcie_aer_log, PCIEAERLog),
115         VMSTATE_MSIX_TEST(parent_obj.parent_obj.parent_obj.parent_obj,
116                           GenPCIERootPort,
117                           gen_rp_test_migrate_msix),
118         VMSTATE_END_OF_LIST()
119     }
120 };
121 
122 static Property gen_rp_props[] = {
123     DEFINE_PROP_BOOL("x-migrate-msix", GenPCIERootPort,
124                      migrate_msix, true),
125     DEFINE_PROP_UINT32("bus-reserve", GenPCIERootPort,
126                        res_reserve.bus, -1),
127     DEFINE_PROP_SIZE("io-reserve", GenPCIERootPort,
128                      res_reserve.io, -1),
129     DEFINE_PROP_SIZE("mem-reserve", GenPCIERootPort,
130                      res_reserve.mem_non_pref, -1),
131     DEFINE_PROP_SIZE("pref32-reserve", GenPCIERootPort,
132                      res_reserve.mem_pref_32, -1),
133     DEFINE_PROP_SIZE("pref64-reserve", GenPCIERootPort,
134                      res_reserve.mem_pref_64, -1),
135     DEFINE_PROP_PCIE_LINK_SPEED("x-speed", PCIESlot,
136                                 speed, PCIE_LINK_SPEED_16),
137     DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot,
138                                 width, PCIE_LINK_WIDTH_32),
139     DEFINE_PROP_END_OF_LIST()
140 };
141 
142 static void gen_rp_dev_class_init(ObjectClass *klass, void *data)
143 {
144     DeviceClass *dc = DEVICE_CLASS(klass);
145     PCIDeviceClass *k = PCI_DEVICE_CLASS(klass);
146     PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(klass);
147 
148     k->vendor_id = PCI_VENDOR_ID_REDHAT;
149     k->device_id = PCI_DEVICE_ID_REDHAT_PCIE_RP;
150     dc->desc = "PCI Express Root Port";
151     dc->vmsd = &vmstate_rp_dev;
152     device_class_set_props(dc, gen_rp_props);
153 
154     device_class_set_parent_realize(dc, gen_rp_realize, &rpc->parent_realize);
155 
156     rpc->aer_vector = gen_rp_aer_vector;
157     rpc->interrupts_init = gen_rp_interrupts_init;
158     rpc->interrupts_uninit = gen_rp_interrupts_uninit;
159     rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
160     rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
161 }
162 
163 static const TypeInfo gen_rp_dev_info = {
164     .name          = TYPE_GEN_PCIE_ROOT_PORT,
165     .parent        = TYPE_PCIE_ROOT_PORT,
166     .instance_size = sizeof(GenPCIERootPort),
167     .class_init    = gen_rp_dev_class_init,
168 };
169 
170  static void gen_rp_register_types(void)
171  {
172     type_register_static(&gen_rp_dev_info);
173  }
174  type_init(gen_rp_register_types)
175