xref: /openbmc/qemu/hw/pci-bridge/cxl_root_port.c (revision b14df228)
1 /*
2  * CXL 2.0 Root Port Implementation
3  *
4  * Copyright(C) 2020 Intel Corporation.
5  *
6  * This library is free software; you can redistribute it and/or
7  * modify it under the terms of the GNU Lesser General Public
8  * License as published by the Free Software Foundation; either
9  * version 2 of the License, or (at your option) any later version.
10  *
11  * This library is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
14  * Lesser General Public License for more details.
15  *
16  * You should have received a copy of the GNU Lesser General Public
17  * License along with this library; if not, see <http://www.gnu.org/licenses/>
18  */
19 
20 #include "qemu/osdep.h"
21 #include "qemu/log.h"
22 #include "qemu/range.h"
23 #include "hw/pci/pci_bridge.h"
24 #include "hw/pci/pcie_port.h"
25 #include "hw/qdev-properties.h"
26 #include "hw/sysbus.h"
27 #include "qapi/error.h"
28 #include "hw/cxl/cxl.h"
29 
30 #define CXL_ROOT_PORT_DID 0x7075
31 
32 /* Copied from the gen root port which we derive */
33 #define GEN_PCIE_ROOT_PORT_AER_OFFSET 0x100
34 #define GEN_PCIE_ROOT_PORT_ACS_OFFSET \
35     (GEN_PCIE_ROOT_PORT_AER_OFFSET + PCI_ERR_SIZEOF)
36 #define CXL_ROOT_PORT_DVSEC_OFFSET \
37     (GEN_PCIE_ROOT_PORT_ACS_OFFSET + PCI_ACS_SIZEOF)
38 
39 typedef struct CXLRootPort {
40     /*< private >*/
41     PCIESlot parent_obj;
42 
43     CXLComponentState cxl_cstate;
44     PCIResReserve res_reserve;
45 } CXLRootPort;
46 
47 #define TYPE_CXL_ROOT_PORT "cxl-rp"
48 DECLARE_INSTANCE_CHECKER(CXLRootPort, CXL_ROOT_PORT, TYPE_CXL_ROOT_PORT)
49 
50 static void latch_registers(CXLRootPort *crp)
51 {
52     uint32_t *reg_state = crp->cxl_cstate.crb.cache_mem_registers;
53     uint32_t *write_msk = crp->cxl_cstate.crb.cache_mem_regs_write_mask;
54 
55     cxl_component_register_init_common(reg_state, write_msk, CXL2_ROOT_PORT);
56 }
57 
58 static void build_dvsecs(CXLComponentState *cxl)
59 {
60     uint8_t *dvsec;
61 
62     dvsec = (uint8_t *)&(CXLDVSECPortExtensions){ 0 };
63     cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
64                                EXTENSIONS_PORT_DVSEC_LENGTH,
65                                EXTENSIONS_PORT_DVSEC,
66                                EXTENSIONS_PORT_DVSEC_REVID, dvsec);
67 
68     dvsec = (uint8_t *)&(CXLDVSECPortGPF){
69         .rsvd        = 0,
70         .phase1_ctrl = 1, /* 1μs timeout */
71         .phase2_ctrl = 1, /* 1μs timeout */
72     };
73     cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
74                                GPF_PORT_DVSEC_LENGTH, GPF_PORT_DVSEC,
75                                GPF_PORT_DVSEC_REVID, dvsec);
76 
77     dvsec = (uint8_t *)&(CXLDVSECPortFlexBus){
78         .cap                     = 0x26, /* IO, Mem, non-MLD */
79         .ctrl                    = 0x2,
80         .status                  = 0x26, /* same */
81         .rcvd_mod_ts_data_phase1 = 0xef,
82     };
83     cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
84                                PCIE_FLEXBUS_PORT_DVSEC_LENGTH_2_0,
85                                PCIE_FLEXBUS_PORT_DVSEC,
86                                PCIE_FLEXBUS_PORT_DVSEC_REVID_2_0, dvsec);
87 
88     dvsec = (uint8_t *)&(CXLDVSECRegisterLocator){
89         .rsvd         = 0,
90         .reg0_base_lo = RBI_COMPONENT_REG | CXL_COMPONENT_REG_BAR_IDX,
91         .reg0_base_hi = 0,
92     };
93     cxl_component_create_dvsec(cxl, CXL2_ROOT_PORT,
94                                REG_LOC_DVSEC_LENGTH, REG_LOC_DVSEC,
95                                REG_LOC_DVSEC_REVID, dvsec);
96 }
97 
98 static void cxl_rp_realize(DeviceState *dev, Error **errp)
99 {
100     PCIDevice *pci_dev     = PCI_DEVICE(dev);
101     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
102     CXLRootPort *crp       = CXL_ROOT_PORT(dev);
103     CXLComponentState *cxl_cstate = &crp->cxl_cstate;
104     ComponentRegisters *cregs = &cxl_cstate->crb;
105     MemoryRegion *component_bar = &cregs->component_registers;
106     Error *local_err = NULL;
107 
108     rpc->parent_realize(dev, &local_err);
109     if (local_err) {
110         error_propagate(errp, local_err);
111         return;
112     }
113 
114     int rc =
115         pci_bridge_qemu_reserve_cap_init(pci_dev, 0, crp->res_reserve, errp);
116     if (rc < 0) {
117         rpc->parent_class.exit(pci_dev);
118         return;
119     }
120 
121     if (!crp->res_reserve.io || crp->res_reserve.io == -1) {
122         pci_word_test_and_clear_mask(pci_dev->wmask + PCI_COMMAND,
123                                      PCI_COMMAND_IO);
124         pci_dev->wmask[PCI_IO_BASE]  = 0;
125         pci_dev->wmask[PCI_IO_LIMIT] = 0;
126     }
127 
128     cxl_cstate->dvsec_offset = CXL_ROOT_PORT_DVSEC_OFFSET;
129     cxl_cstate->pdev = pci_dev;
130     build_dvsecs(&crp->cxl_cstate);
131 
132     cxl_component_register_block_init(OBJECT(pci_dev), cxl_cstate,
133                                       TYPE_CXL_ROOT_PORT);
134 
135     pci_register_bar(pci_dev, CXL_COMPONENT_REG_BAR_IDX,
136                      PCI_BASE_ADDRESS_SPACE_MEMORY |
137                          PCI_BASE_ADDRESS_MEM_TYPE_64,
138                      component_bar);
139 }
140 
141 static void cxl_rp_reset(DeviceState *dev)
142 {
143     PCIERootPortClass *rpc = PCIE_ROOT_PORT_GET_CLASS(dev);
144     CXLRootPort *crp = CXL_ROOT_PORT(dev);
145 
146     rpc->parent_reset(dev);
147 
148     latch_registers(crp);
149 }
150 
151 static Property gen_rp_props[] = {
152     DEFINE_PROP_UINT32("bus-reserve", CXLRootPort, res_reserve.bus, -1),
153     DEFINE_PROP_SIZE("io-reserve", CXLRootPort, res_reserve.io, -1),
154     DEFINE_PROP_SIZE("mem-reserve", CXLRootPort, res_reserve.mem_non_pref, -1),
155     DEFINE_PROP_SIZE("pref32-reserve", CXLRootPort, res_reserve.mem_pref_32,
156                      -1),
157     DEFINE_PROP_SIZE("pref64-reserve", CXLRootPort, res_reserve.mem_pref_64,
158                      -1),
159     DEFINE_PROP_END_OF_LIST()
160 };
161 
162 static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr,
163                                       uint32_t val, int len)
164 {
165     CXLRootPort *crp = CXL_ROOT_PORT(dev);
166 
167     if (range_contains(&crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC], addr)) {
168         uint8_t *reg = &dev->config[addr];
169         addr -= crp->cxl_cstate.dvsecs[EXTENSIONS_PORT_DVSEC].lob;
170         if (addr == PORT_CONTROL_OFFSET) {
171             if (pci_get_word(reg) & PORT_CONTROL_UNMASK_SBR) {
172                 /* unmask SBR */
173                 qemu_log_mask(LOG_UNIMP, "SBR mask control is not supported\n");
174             }
175             if (pci_get_word(reg) & PORT_CONTROL_ALT_MEMID_EN) {
176                 /* Alt Memory & ID Space Enable */
177                 qemu_log_mask(LOG_UNIMP,
178                               "Alt Memory & ID space is not supported\n");
179             }
180         }
181     }
182 }
183 
184 static void cxl_rp_write_config(PCIDevice *d, uint32_t address, uint32_t val,
185                                 int len)
186 {
187     uint16_t slt_ctl, slt_sta;
188 
189     pcie_cap_slot_get(d, &slt_ctl, &slt_sta);
190     pci_bridge_write_config(d, address, val, len);
191     pcie_cap_flr_write_config(d, address, val, len);
192     pcie_cap_slot_write_config(d, slt_ctl, slt_sta, address, val, len);
193     pcie_aer_write_config(d, address, val, len);
194 
195     cxl_rp_dvsec_write_config(d, address, val, len);
196 }
197 
198 static void cxl_root_port_class_init(ObjectClass *oc, void *data)
199 {
200     DeviceClass *dc        = DEVICE_CLASS(oc);
201     PCIDeviceClass *k      = PCI_DEVICE_CLASS(oc);
202     PCIERootPortClass *rpc = PCIE_ROOT_PORT_CLASS(oc);
203 
204     k->vendor_id = PCI_VENDOR_ID_INTEL;
205     k->device_id = CXL_ROOT_PORT_DID;
206     dc->desc     = "CXL Root Port";
207     k->revision  = 0;
208     device_class_set_props(dc, gen_rp_props);
209     k->config_write = cxl_rp_write_config;
210 
211     device_class_set_parent_realize(dc, cxl_rp_realize, &rpc->parent_realize);
212     device_class_set_parent_reset(dc, cxl_rp_reset, &rpc->parent_reset);
213 
214     rpc->aer_offset = GEN_PCIE_ROOT_PORT_AER_OFFSET;
215     rpc->acs_offset = GEN_PCIE_ROOT_PORT_ACS_OFFSET;
216 
217     dc->hotpluggable = false;
218 }
219 
220 static const TypeInfo cxl_root_port_info = {
221     .name = TYPE_CXL_ROOT_PORT,
222     .parent = TYPE_PCIE_ROOT_PORT,
223     .instance_size = sizeof(CXLRootPort),
224     .class_init = cxl_root_port_class_init,
225     .interfaces = (InterfaceInfo[]) {
226         { INTERFACE_CXL_DEVICE },
227         { }
228     },
229 };
230 
231 static void cxl_register(void)
232 {
233     type_register_static(&cxl_root_port_info);
234 }
235 
236 type_init(cxl_register);
237