1 /* 2 * SPDX-License-Identifier: GPL-2.0-or-later 3 * 4 * OpenRISC QEMU virtual machine. 5 * 6 * (c) 2022 Stafford Horne <shorne@gmail.com> 7 */ 8 9 #include "qemu/osdep.h" 10 #include "qemu/error-report.h" 11 #include "qapi/error.h" 12 #include "cpu.h" 13 #include "exec/address-spaces.h" 14 #include "hw/irq.h" 15 #include "hw/boards.h" 16 #include "hw/char/serial.h" 17 #include "hw/core/split-irq.h" 18 #include "hw/openrisc/boot.h" 19 #include "hw/misc/sifive_test.h" 20 #include "hw/pci/pci.h" 21 #include "hw/pci-host/gpex.h" 22 #include "hw/qdev-properties.h" 23 #include "hw/rtc/goldfish_rtc.h" 24 #include "hw/sysbus.h" 25 #include "hw/virtio/virtio-mmio.h" 26 #include "sysemu/device_tree.h" 27 #include "sysemu/sysemu.h" 28 #include "sysemu/qtest.h" 29 #include "sysemu/reset.h" 30 31 #include <libfdt.h> 32 33 #define VIRT_CPUS_MAX 4 34 #define VIRT_CLK_MHZ 20000000 35 36 #define TYPE_VIRT_MACHINE MACHINE_TYPE_NAME("virt") 37 #define VIRT_MACHINE(obj) \ 38 OBJECT_CHECK(OR1KVirtState, (obj), TYPE_VIRT_MACHINE) 39 40 typedef struct OR1KVirtState { 41 /*< private >*/ 42 MachineState parent_obj; 43 44 /*< public >*/ 45 void *fdt; 46 int fdt_size; 47 48 } OR1KVirtState; 49 50 enum { 51 VIRT_DRAM, 52 VIRT_ECAM, 53 VIRT_MMIO, 54 VIRT_PIO, 55 VIRT_TEST, 56 VIRT_RTC, 57 VIRT_VIRTIO, 58 VIRT_UART, 59 VIRT_OMPIC, 60 }; 61 62 enum { 63 VIRT_OMPIC_IRQ = 1, 64 VIRT_UART_IRQ = 2, 65 VIRT_RTC_IRQ = 3, 66 VIRT_VIRTIO_IRQ = 4, /* to 12 */ 67 VIRTIO_COUNT = 8, 68 VIRT_PCI_IRQ_BASE = 13, /* to 17 */ 69 }; 70 71 static const struct MemmapEntry { 72 hwaddr base; 73 hwaddr size; 74 } virt_memmap[] = { 75 [VIRT_DRAM] = { 0x00000000, 0 }, 76 [VIRT_UART] = { 0x90000000, 0x100 }, 77 [VIRT_TEST] = { 0x96000000, 0x8 }, 78 [VIRT_RTC] = { 0x96005000, 0x1000 }, 79 [VIRT_VIRTIO] = { 0x97000000, 0x1000 }, 80 [VIRT_OMPIC] = { 0x98000000, VIRT_CPUS_MAX * 8 }, 81 [VIRT_ECAM] = { 0x9e000000, 0x1000000 }, 82 [VIRT_PIO] = { 0x9f000000, 0x1000000 }, 83 [VIRT_MMIO] = { 0xa0000000, 0x10000000 }, 84 }; 85 86 static struct openrisc_boot_info { 87 uint32_t bootstrap_pc; 88 uint32_t fdt_addr; 89 } boot_info; 90 91 static void main_cpu_reset(void *opaque) 92 { 93 OpenRISCCPU *cpu = opaque; 94 CPUState *cs = CPU(cpu); 95 96 cpu_reset(CPU(cpu)); 97 98 cpu_set_pc(cs, boot_info.bootstrap_pc); 99 cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr); 100 } 101 102 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) 103 { 104 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); 105 } 106 107 static qemu_irq get_per_cpu_irq(OpenRISCCPU *cpus[], int num_cpus, int irq_pin) 108 { 109 int i; 110 111 if (num_cpus > 1) { 112 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 113 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 114 qdev_realize_and_unref(splitter, NULL, &error_fatal); 115 for (i = 0; i < num_cpus; i++) { 116 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 117 } 118 return qdev_get_gpio_in(splitter, 0); 119 } else { 120 return get_cpu_irq(cpus, 0, irq_pin); 121 } 122 } 123 124 static void openrisc_create_fdt(OR1KVirtState *state, 125 const struct MemmapEntry *memmap, 126 int num_cpus, uint64_t mem_size, 127 const char *cmdline, 128 int32_t *pic_phandle) 129 { 130 void *fdt; 131 int cpu; 132 char *nodename; 133 134 fdt = state->fdt = create_device_tree(&state->fdt_size); 135 if (!fdt) { 136 error_report("create_device_tree() failed"); 137 exit(1); 138 } 139 140 qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim"); 141 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); 142 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); 143 144 qemu_fdt_add_subnode(fdt, "/soc"); 145 qemu_fdt_setprop(fdt, "/soc", "ranges", NULL, 0); 146 qemu_fdt_setprop_string(fdt, "/soc", "compatible", "simple-bus"); 147 qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x1); 148 qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x1); 149 150 nodename = g_strdup_printf("/memory@%" HWADDR_PRIx, 151 memmap[VIRT_DRAM].base); 152 qemu_fdt_add_subnode(fdt, nodename); 153 qemu_fdt_setprop_cells(fdt, nodename, "reg", 154 memmap[VIRT_DRAM].base, mem_size); 155 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 156 g_free(nodename); 157 158 qemu_fdt_add_subnode(fdt, "/cpus"); 159 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 160 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 161 162 for (cpu = 0; cpu < num_cpus; cpu++) { 163 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 164 qemu_fdt_add_subnode(fdt, nodename); 165 qemu_fdt_setprop_string(fdt, nodename, "compatible", 166 "opencores,or1200-rtlsvn481"); 167 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 168 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 169 VIRT_CLK_MHZ); 170 g_free(nodename); 171 } 172 173 nodename = (char *)"/pic"; 174 qemu_fdt_add_subnode(fdt, nodename); 175 *pic_phandle = qemu_fdt_alloc_phandle(fdt); 176 qemu_fdt_setprop_string(fdt, nodename, "compatible", 177 "opencores,or1k-pic-level"); 178 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 179 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 180 qemu_fdt_setprop_cell(fdt, nodename, "phandle", *pic_phandle); 181 182 qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", *pic_phandle); 183 184 qemu_fdt_add_subnode(fdt, "/chosen"); 185 if (cmdline) { 186 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 187 } 188 189 /* Create aliases node for use by devices. */ 190 qemu_fdt_add_subnode(fdt, "/aliases"); 191 } 192 193 static void openrisc_virt_ompic_init(OR1KVirtState *state, hwaddr base, 194 hwaddr size, int num_cpus, 195 OpenRISCCPU *cpus[], int irq_pin) 196 { 197 void *fdt = state->fdt; 198 DeviceState *dev; 199 SysBusDevice *s; 200 char *nodename; 201 int i; 202 203 dev = qdev_new("or1k-ompic"); 204 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 205 206 s = SYS_BUS_DEVICE(dev); 207 sysbus_realize_and_unref(s, &error_fatal); 208 for (i = 0; i < num_cpus; i++) { 209 sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); 210 } 211 sysbus_mmio_map(s, 0, base); 212 213 /* Add device tree node for ompic. */ 214 nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base); 215 qemu_fdt_add_subnode(fdt, nodename); 216 qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic"); 217 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 218 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 219 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0); 220 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 221 g_free(nodename); 222 } 223 224 static void openrisc_virt_serial_init(OR1KVirtState *state, hwaddr base, 225 hwaddr size, int num_cpus, 226 OpenRISCCPU *cpus[], int irq_pin) 227 { 228 void *fdt = state->fdt; 229 char *nodename; 230 qemu_irq serial_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin); 231 232 serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, 233 serial_hd(0), DEVICE_NATIVE_ENDIAN); 234 235 /* Add device tree node for serial. */ 236 nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base); 237 qemu_fdt_add_subnode(fdt, nodename); 238 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); 239 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 240 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 241 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", VIRT_CLK_MHZ); 242 qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); 243 244 /* The /chosen node is created during fdt creation. */ 245 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 246 qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename); 247 g_free(nodename); 248 } 249 250 static void openrisc_virt_test_init(OR1KVirtState *state, hwaddr base, 251 hwaddr size) 252 { 253 void *fdt = state->fdt; 254 int test_ph; 255 char *nodename; 256 257 /* SiFive Test MMIO device */ 258 sifive_test_create(base); 259 260 /* SiFive Test MMIO Reset device FDT */ 261 nodename = g_strdup_printf("/soc/test@%" HWADDR_PRIx, base); 262 qemu_fdt_add_subnode(fdt, nodename); 263 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon"); 264 test_ph = qemu_fdt_alloc_phandle(fdt); 265 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 266 qemu_fdt_setprop_cell(fdt, nodename, "phandle", test_ph); 267 qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); 268 g_free(nodename); 269 270 nodename = g_strdup_printf("/soc/reboot"); 271 qemu_fdt_add_subnode(fdt, nodename); 272 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-reboot"); 273 qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph); 274 qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); 275 qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_RESET); 276 g_free(nodename); 277 278 nodename = g_strdup_printf("/soc/poweroff"); 279 qemu_fdt_add_subnode(fdt, nodename); 280 qemu_fdt_setprop_string(fdt, nodename, "compatible", "syscon-poweroff"); 281 qemu_fdt_setprop_cell(fdt, nodename, "regmap", test_ph); 282 qemu_fdt_setprop_cell(fdt, nodename, "offset", 0x0); 283 qemu_fdt_setprop_cell(fdt, nodename, "value", FINISHER_PASS); 284 g_free(nodename); 285 286 } 287 288 static void openrisc_virt_rtc_init(OR1KVirtState *state, hwaddr base, 289 hwaddr size, int num_cpus, 290 OpenRISCCPU *cpus[], int irq_pin) 291 { 292 void *fdt = state->fdt; 293 char *nodename; 294 qemu_irq rtc_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin); 295 296 /* Goldfish RTC */ 297 sysbus_create_simple(TYPE_GOLDFISH_RTC, base, rtc_irq); 298 299 /* Goldfish RTC FDT */ 300 nodename = g_strdup_printf("/soc/rtc@%" HWADDR_PRIx, base); 301 qemu_fdt_add_subnode(fdt, nodename); 302 qemu_fdt_setprop_string(fdt, nodename, "compatible", 303 "google,goldfish-rtc"); 304 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 305 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 306 g_free(nodename); 307 308 } 309 310 static void create_pcie_irq_map(void *fdt, char *nodename, int irq_base, 311 uint32_t irqchip_phandle) 312 { 313 int pin, dev; 314 uint32_t irq_map_stride = 0; 315 uint32_t full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * 6] = {}; 316 uint32_t *irq_map = full_irq_map; 317 318 /* 319 * This code creates a standard swizzle of interrupts such that 320 * each device's first interrupt is based on it's PCI_SLOT number. 321 * (See pci_swizzle_map_irq_fn()) 322 * 323 * We only need one entry per interrupt in the table (not one per 324 * possible slot) seeing the interrupt-map-mask will allow the table 325 * to wrap to any number of devices. 326 */ 327 for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { 328 int devfn = dev << 3; 329 330 for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { 331 int irq_nr = irq_base + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); 332 int i = 0; 333 334 /* Fill PCI address cells */ 335 irq_map[i++] = cpu_to_be32(devfn << 8); 336 irq_map[i++] = 0; 337 irq_map[i++] = 0; 338 339 /* Fill PCI Interrupt cells */ 340 irq_map[i++] = cpu_to_be32(pin + 1); 341 342 /* Fill interrupt controller phandle and cells */ 343 irq_map[i++] = cpu_to_be32(irqchip_phandle); 344 irq_map[i++] = cpu_to_be32(irq_nr); 345 346 if (!irq_map_stride) { 347 irq_map_stride = i; 348 } 349 irq_map += irq_map_stride; 350 } 351 } 352 353 qemu_fdt_setprop(fdt, nodename, "interrupt-map", full_irq_map, 354 GPEX_NUM_IRQS * GPEX_NUM_IRQS * 355 irq_map_stride * sizeof(uint32_t)); 356 357 qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", 358 0x1800, 0, 0, 0x7); 359 } 360 361 static void openrisc_virt_pcie_init(OR1KVirtState *state, 362 hwaddr ecam_base, hwaddr ecam_size, 363 hwaddr pio_base, hwaddr pio_size, 364 hwaddr mmio_base, hwaddr mmio_size, 365 int num_cpus, OpenRISCCPU *cpus[], 366 int irq_base, int32_t pic_phandle) 367 { 368 void *fdt = state->fdt; 369 char *nodename; 370 MemoryRegion *alias; 371 MemoryRegion *reg; 372 DeviceState *dev; 373 qemu_irq pcie_irq; 374 int i; 375 376 dev = qdev_new(TYPE_GPEX_HOST); 377 sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); 378 379 /* Map ECAM space. */ 380 alias = g_new0(MemoryRegion, 1); 381 reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); 382 memory_region_init_alias(alias, OBJECT(dev), "pcie-ecam", 383 reg, 0, ecam_size); 384 memory_region_add_subregion(get_system_memory(), ecam_base, alias); 385 386 /* 387 * Map the MMIO window into system address space so as to expose 388 * the section of PCI MMIO space which starts at the same base address 389 * (ie 1:1 mapping for that part of PCI MMIO space visible through 390 * the window). 391 */ 392 alias = g_new0(MemoryRegion, 1); 393 reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); 394 memory_region_init_alias(alias, OBJECT(dev), "pcie-mmio", 395 reg, mmio_base, mmio_size); 396 memory_region_add_subregion(get_system_memory(), mmio_base, alias); 397 398 /* Map IO port space. */ 399 alias = g_new0(MemoryRegion, 1); 400 reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 2); 401 memory_region_init_alias(alias, OBJECT(dev), "pcie-pio", 402 reg, 0, pio_size); 403 memory_region_add_subregion(get_system_memory(), pio_base, alias); 404 405 /* Connect IRQ lines. */ 406 for (i = 0; i < GPEX_NUM_IRQS; i++) { 407 pcie_irq = get_per_cpu_irq(cpus, num_cpus, irq_base + i); 408 409 sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, pcie_irq); 410 gpex_set_irq_num(GPEX_HOST(dev), i, irq_base + i); 411 } 412 413 nodename = g_strdup_printf("/soc/pci@%" HWADDR_PRIx, ecam_base); 414 qemu_fdt_add_subnode(fdt, nodename); 415 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 416 qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 3); 417 qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 2); 418 qemu_fdt_setprop_string(fdt, nodename, "compatible", 419 "pci-host-ecam-generic"); 420 qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); 421 qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); 422 qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, 423 ecam_size / PCIE_MMCFG_SIZE_MIN - 1); 424 qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); 425 qemu_fdt_setprop_cells(fdt, nodename, "reg", ecam_base, ecam_size); 426 /* pci-address(3) cpu-address(1) pci-size(2) */ 427 qemu_fdt_setprop_cells(fdt, nodename, "ranges", 428 FDT_PCI_RANGE_IOPORT, 0, 0, 429 pio_base, 0, pio_size, 430 FDT_PCI_RANGE_MMIO, 0, mmio_base, 431 mmio_base, 0, mmio_size); 432 433 create_pcie_irq_map(fdt, nodename, irq_base, pic_phandle); 434 g_free(nodename); 435 } 436 437 static void openrisc_virt_virtio_init(OR1KVirtState *state, hwaddr base, 438 hwaddr size, int num_cpus, 439 OpenRISCCPU *cpus[], int irq_pin) 440 { 441 void *fdt = state->fdt; 442 char *nodename; 443 DeviceState *dev; 444 SysBusDevice *sysbus; 445 qemu_irq virtio_irq = get_per_cpu_irq(cpus, num_cpus, irq_pin); 446 447 /* VirtIO MMIO devices */ 448 dev = qdev_new(TYPE_VIRTIO_MMIO); 449 qdev_prop_set_bit(dev, "force-legacy", false); 450 sysbus = SYS_BUS_DEVICE(dev); 451 sysbus_realize_and_unref(sysbus, &error_fatal); 452 sysbus_connect_irq(sysbus, 0, virtio_irq); 453 sysbus_mmio_map(sysbus, 0, base); 454 455 /* VirtIO MMIO devices FDT */ 456 nodename = g_strdup_printf("/soc/virtio_mmio@%" HWADDR_PRIx, base); 457 qemu_fdt_add_subnode(fdt, nodename); 458 qemu_fdt_setprop_string(fdt, nodename, "compatible", "virtio,mmio"); 459 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 460 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 461 g_free(nodename); 462 } 463 464 static void openrisc_virt_init(MachineState *machine) 465 { 466 ram_addr_t ram_size = machine->ram_size; 467 const char *kernel_filename = machine->kernel_filename; 468 OpenRISCCPU *cpus[VIRT_CPUS_MAX] = {}; 469 OR1KVirtState *state = VIRT_MACHINE(machine); 470 MemoryRegion *ram; 471 hwaddr load_addr; 472 int n; 473 unsigned int smp_cpus = machine->smp.cpus; 474 int32_t pic_phandle; 475 476 assert(smp_cpus >= 1 && smp_cpus <= VIRT_CPUS_MAX); 477 for (n = 0; n < smp_cpus; n++) { 478 cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); 479 if (cpus[n] == NULL) { 480 fprintf(stderr, "Unable to find CPU definition!\n"); 481 exit(1); 482 } 483 484 cpu_openrisc_clock_init(cpus[n]); 485 486 qemu_register_reset(main_cpu_reset, cpus[n]); 487 } 488 489 ram = g_malloc(sizeof(*ram)); 490 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 491 memory_region_add_subregion(get_system_memory(), 0, ram); 492 493 openrisc_create_fdt(state, virt_memmap, smp_cpus, machine->ram_size, 494 machine->kernel_cmdline, &pic_phandle); 495 496 if (smp_cpus > 1) { 497 openrisc_virt_ompic_init(state, virt_memmap[VIRT_OMPIC].base, 498 virt_memmap[VIRT_OMPIC].size, 499 smp_cpus, cpus, VIRT_OMPIC_IRQ); 500 } 501 502 openrisc_virt_serial_init(state, virt_memmap[VIRT_UART].base, 503 virt_memmap[VIRT_UART].size, 504 smp_cpus, cpus, VIRT_UART_IRQ); 505 506 openrisc_virt_test_init(state, virt_memmap[VIRT_TEST].base, 507 virt_memmap[VIRT_TEST].size); 508 509 openrisc_virt_rtc_init(state, virt_memmap[VIRT_RTC].base, 510 virt_memmap[VIRT_RTC].size, smp_cpus, cpus, 511 VIRT_RTC_IRQ); 512 513 openrisc_virt_pcie_init(state, virt_memmap[VIRT_ECAM].base, 514 virt_memmap[VIRT_ECAM].size, 515 virt_memmap[VIRT_PIO].base, 516 virt_memmap[VIRT_PIO].size, 517 virt_memmap[VIRT_MMIO].base, 518 virt_memmap[VIRT_MMIO].size, 519 smp_cpus, cpus, 520 VIRT_PCI_IRQ_BASE, pic_phandle); 521 522 for (n = 0; n < VIRTIO_COUNT; n++) { 523 openrisc_virt_virtio_init(state, virt_memmap[VIRT_VIRTIO].base 524 + n * virt_memmap[VIRT_VIRTIO].size, 525 virt_memmap[VIRT_VIRTIO].size, 526 smp_cpus, cpus, VIRT_VIRTIO_IRQ + n); 527 } 528 529 load_addr = openrisc_load_kernel(ram_size, kernel_filename, 530 &boot_info.bootstrap_pc); 531 if (load_addr > 0) { 532 if (machine->initrd_filename) { 533 load_addr = openrisc_load_initrd(state->fdt, 534 machine->initrd_filename, 535 load_addr, machine->ram_size); 536 } 537 boot_info.fdt_addr = openrisc_load_fdt(state->fdt, load_addr, 538 machine->ram_size); 539 } 540 } 541 542 static void openrisc_virt_machine_init(ObjectClass *oc, void *data) 543 { 544 MachineClass *mc = MACHINE_CLASS(oc); 545 546 mc->desc = "or1k virtual machine"; 547 mc->init = openrisc_virt_init; 548 mc->max_cpus = VIRT_CPUS_MAX; 549 mc->is_default = false; 550 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 551 } 552 553 static const TypeInfo or1ksim_machine_typeinfo = { 554 .name = TYPE_VIRT_MACHINE, 555 .parent = TYPE_MACHINE, 556 .class_init = openrisc_virt_machine_init, 557 .instance_size = sizeof(OR1KVirtState), 558 }; 559 560 static void or1ksim_machine_init_register_types(void) 561 { 562 type_register_static(&or1ksim_machine_typeinfo); 563 } 564 565 type_init(or1ksim_machine_init_register_types) 566