1 /* 2 * OpenRISC simulator for use as an IIS. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/irq.h" 26 #include "hw/boards.h" 27 #include "elf.h" 28 #include "hw/char/serial.h" 29 #include "net/net.h" 30 #include "hw/loader.h" 31 #include "hw/qdev-properties.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/sysbus.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "hw/core/split-irq.h" 37 38 #define KERNEL_LOAD_ADDR 0x100 39 40 #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim") 41 #define OR1KSIM_MACHINE(obj) \ 42 OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE) 43 44 typedef struct Or1ksimState { 45 /*< private >*/ 46 MachineState parent_obj; 47 48 /*< public >*/ 49 50 } Or1ksimState; 51 52 static struct openrisc_boot_info { 53 uint32_t bootstrap_pc; 54 } boot_info; 55 56 static void main_cpu_reset(void *opaque) 57 { 58 OpenRISCCPU *cpu = opaque; 59 CPUState *cs = CPU(cpu); 60 61 cpu_reset(CPU(cpu)); 62 63 cpu_set_pc(cs, boot_info.bootstrap_pc); 64 } 65 66 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) 67 { 68 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); 69 } 70 71 static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, 72 int num_cpus, OpenRISCCPU *cpus[], 73 int irq_pin, NICInfo *nd) 74 { 75 DeviceState *dev; 76 SysBusDevice *s; 77 int i; 78 79 dev = qdev_new("open_eth"); 80 qdev_set_nic_properties(dev, nd); 81 82 s = SYS_BUS_DEVICE(dev); 83 sysbus_realize_and_unref(s, &error_fatal); 84 if (num_cpus > 1) { 85 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 86 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 87 qdev_realize_and_unref(splitter, NULL, &error_fatal); 88 for (i = 0; i < num_cpus; i++) { 89 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 90 } 91 sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); 92 } else { 93 sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); 94 } 95 sysbus_mmio_map(s, 0, base); 96 sysbus_mmio_map(s, 1, descriptors); 97 } 98 99 static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, 100 OpenRISCCPU *cpus[], int irq_pin) 101 { 102 DeviceState *dev; 103 SysBusDevice *s; 104 int i; 105 106 dev = qdev_new("or1k-ompic"); 107 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 108 109 s = SYS_BUS_DEVICE(dev); 110 sysbus_realize_and_unref(s, &error_fatal); 111 for (i = 0; i < num_cpus; i++) { 112 sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); 113 } 114 sysbus_mmio_map(s, 0, base); 115 } 116 117 static void openrisc_load_kernel(ram_addr_t ram_size, 118 const char *kernel_filename) 119 { 120 long kernel_size; 121 uint64_t elf_entry; 122 hwaddr entry; 123 124 if (kernel_filename && !qtest_enabled()) { 125 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 126 &elf_entry, NULL, NULL, NULL, 1, EM_OPENRISC, 127 1, 0); 128 entry = elf_entry; 129 if (kernel_size < 0) { 130 kernel_size = load_uimage(kernel_filename, 131 &entry, NULL, NULL, NULL, NULL); 132 } 133 if (kernel_size < 0) { 134 kernel_size = load_image_targphys(kernel_filename, 135 KERNEL_LOAD_ADDR, 136 ram_size - KERNEL_LOAD_ADDR); 137 } 138 139 if (entry <= 0) { 140 entry = KERNEL_LOAD_ADDR; 141 } 142 143 if (kernel_size < 0) { 144 error_report("couldn't load the kernel '%s'", kernel_filename); 145 exit(1); 146 } 147 boot_info.bootstrap_pc = entry; 148 } 149 } 150 151 static void openrisc_sim_init(MachineState *machine) 152 { 153 ram_addr_t ram_size = machine->ram_size; 154 const char *kernel_filename = machine->kernel_filename; 155 OpenRISCCPU *cpus[2] = {}; 156 MemoryRegion *ram; 157 qemu_irq serial_irq; 158 int n; 159 unsigned int smp_cpus = machine->smp.cpus; 160 161 assert(smp_cpus >= 1 && smp_cpus <= 2); 162 for (n = 0; n < smp_cpus; n++) { 163 cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); 164 if (cpus[n] == NULL) { 165 fprintf(stderr, "Unable to find CPU definition!\n"); 166 exit(1); 167 } 168 169 cpu_openrisc_clock_init(cpus[n]); 170 171 qemu_register_reset(main_cpu_reset, cpus[n]); 172 } 173 174 ram = g_malloc(sizeof(*ram)); 175 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 176 memory_region_add_subregion(get_system_memory(), 0, ram); 177 178 if (nd_table[0].used) { 179 openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, 180 cpus, 4, nd_table); 181 } 182 183 if (smp_cpus > 1) { 184 openrisc_sim_ompic_init(0x98000000, smp_cpus, cpus, 1); 185 186 serial_irq = qemu_irq_split(get_cpu_irq(cpus, 0, 2), 187 get_cpu_irq(cpus, 1, 2)); 188 } else { 189 serial_irq = get_cpu_irq(cpus, 0, 2); 190 } 191 192 serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, 193 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 194 195 openrisc_load_kernel(ram_size, kernel_filename); 196 } 197 198 static void openrisc_sim_machine_init(ObjectClass *oc, void *data) 199 { 200 MachineClass *mc = MACHINE_CLASS(oc); 201 202 mc->desc = "or1k simulation"; 203 mc->init = openrisc_sim_init; 204 mc->max_cpus = 2; 205 mc->is_default = true; 206 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 207 } 208 209 static const TypeInfo or1ksim_machine_typeinfo = { 210 .name = TYPE_OR1KSIM_MACHINE, 211 .parent = TYPE_MACHINE, 212 .class_init = openrisc_sim_machine_init, 213 .instance_size = sizeof(Or1ksimState), 214 }; 215 216 static void or1ksim_machine_init_register_types(void) 217 { 218 type_register_static(&or1ksim_machine_typeinfo); 219 } 220 221 type_init(or1ksim_machine_init_register_types) 222