1 /* 2 * OpenRISC simulator for use as an IIS. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/irq.h" 26 #include "hw/boards.h" 27 #include "elf.h" 28 #include "hw/char/serial.h" 29 #include "net/net.h" 30 #include "hw/loader.h" 31 #include "hw/qdev-properties.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/sysbus.h" 34 #include "sysemu/qtest.h" 35 #include "sysemu/reset.h" 36 #include "hw/core/split-irq.h" 37 38 #define KERNEL_LOAD_ADDR 0x100 39 40 #define OR1KSIM_CPUS_MAX 4 41 42 #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim") 43 #define OR1KSIM_MACHINE(obj) \ 44 OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE) 45 46 typedef struct Or1ksimState { 47 /*< private >*/ 48 MachineState parent_obj; 49 50 /*< public >*/ 51 52 } Or1ksimState; 53 54 enum { 55 OR1KSIM_DRAM, 56 OR1KSIM_UART, 57 OR1KSIM_ETHOC, 58 OR1KSIM_OMPIC, 59 }; 60 61 enum { 62 OR1KSIM_OMPIC_IRQ = 1, 63 OR1KSIM_UART_IRQ = 2, 64 OR1KSIM_ETHOC_IRQ = 4, 65 }; 66 67 static const struct MemmapEntry { 68 hwaddr base; 69 hwaddr size; 70 } or1ksim_memmap[] = { 71 [OR1KSIM_DRAM] = { 0x00000000, 0 }, 72 [OR1KSIM_UART] = { 0x90000000, 0x100 }, 73 [OR1KSIM_ETHOC] = { 0x92000000, 0x800 }, 74 [OR1KSIM_OMPIC] = { 0x98000000, 16 }, 75 }; 76 77 static struct openrisc_boot_info { 78 uint32_t bootstrap_pc; 79 } boot_info; 80 81 static void main_cpu_reset(void *opaque) 82 { 83 OpenRISCCPU *cpu = opaque; 84 CPUState *cs = CPU(cpu); 85 86 cpu_reset(CPU(cpu)); 87 88 cpu_set_pc(cs, boot_info.bootstrap_pc); 89 } 90 91 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) 92 { 93 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); 94 } 95 96 static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, 97 int num_cpus, OpenRISCCPU *cpus[], 98 int irq_pin, NICInfo *nd) 99 { 100 DeviceState *dev; 101 SysBusDevice *s; 102 int i; 103 104 dev = qdev_new("open_eth"); 105 qdev_set_nic_properties(dev, nd); 106 107 s = SYS_BUS_DEVICE(dev); 108 sysbus_realize_and_unref(s, &error_fatal); 109 if (num_cpus > 1) { 110 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 111 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 112 qdev_realize_and_unref(splitter, NULL, &error_fatal); 113 for (i = 0; i < num_cpus; i++) { 114 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 115 } 116 sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); 117 } else { 118 sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); 119 } 120 sysbus_mmio_map(s, 0, base); 121 sysbus_mmio_map(s, 1, descriptors); 122 } 123 124 static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, 125 OpenRISCCPU *cpus[], int irq_pin) 126 { 127 DeviceState *dev; 128 SysBusDevice *s; 129 int i; 130 131 dev = qdev_new("or1k-ompic"); 132 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 133 134 s = SYS_BUS_DEVICE(dev); 135 sysbus_realize_and_unref(s, &error_fatal); 136 for (i = 0; i < num_cpus; i++) { 137 sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); 138 } 139 sysbus_mmio_map(s, 0, base); 140 } 141 142 static void openrisc_sim_serial_init(hwaddr base, int num_cpus, 143 OpenRISCCPU *cpus[], int irq_pin) 144 { 145 qemu_irq serial_irq; 146 int i; 147 148 if (num_cpus > 1) { 149 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 150 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 151 qdev_realize_and_unref(splitter, NULL, &error_fatal); 152 for (i = 0; i < num_cpus; i++) { 153 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 154 } 155 serial_irq = qdev_get_gpio_in(splitter, 0); 156 } else { 157 serial_irq = get_cpu_irq(cpus, 0, irq_pin); 158 } 159 serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, 160 serial_hd(0), DEVICE_NATIVE_ENDIAN); 161 } 162 163 164 static void openrisc_load_kernel(ram_addr_t ram_size, 165 const char *kernel_filename) 166 { 167 long kernel_size; 168 uint64_t elf_entry; 169 hwaddr entry; 170 171 if (kernel_filename && !qtest_enabled()) { 172 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 173 &elf_entry, NULL, NULL, NULL, 1, EM_OPENRISC, 174 1, 0); 175 entry = elf_entry; 176 if (kernel_size < 0) { 177 kernel_size = load_uimage(kernel_filename, 178 &entry, NULL, NULL, NULL, NULL); 179 } 180 if (kernel_size < 0) { 181 kernel_size = load_image_targphys(kernel_filename, 182 KERNEL_LOAD_ADDR, 183 ram_size - KERNEL_LOAD_ADDR); 184 } 185 186 if (entry <= 0) { 187 entry = KERNEL_LOAD_ADDR; 188 } 189 190 if (kernel_size < 0) { 191 error_report("couldn't load the kernel '%s'", kernel_filename); 192 exit(1); 193 } 194 boot_info.bootstrap_pc = entry; 195 } 196 } 197 198 static void openrisc_sim_init(MachineState *machine) 199 { 200 ram_addr_t ram_size = machine->ram_size; 201 const char *kernel_filename = machine->kernel_filename; 202 OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {}; 203 MemoryRegion *ram; 204 int n; 205 unsigned int smp_cpus = machine->smp.cpus; 206 207 assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX); 208 for (n = 0; n < smp_cpus; n++) { 209 cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); 210 if (cpus[n] == NULL) { 211 fprintf(stderr, "Unable to find CPU definition!\n"); 212 exit(1); 213 } 214 215 cpu_openrisc_clock_init(cpus[n]); 216 217 qemu_register_reset(main_cpu_reset, cpus[n]); 218 } 219 220 ram = g_malloc(sizeof(*ram)); 221 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 222 memory_region_add_subregion(get_system_memory(), 0, ram); 223 224 if (nd_table[0].used) { 225 openrisc_sim_net_init(or1ksim_memmap[OR1KSIM_ETHOC].base, 226 or1ksim_memmap[OR1KSIM_ETHOC].base + 0x400, 227 smp_cpus, cpus, 228 OR1KSIM_ETHOC_IRQ, nd_table); 229 } 230 231 if (smp_cpus > 1) { 232 openrisc_sim_ompic_init(or1ksim_memmap[OR1KSIM_OMPIC].base, smp_cpus, 233 cpus, OR1KSIM_OMPIC_IRQ); 234 } 235 236 openrisc_sim_serial_init(or1ksim_memmap[OR1KSIM_UART].base, smp_cpus, cpus, 237 OR1KSIM_UART_IRQ); 238 239 openrisc_load_kernel(ram_size, kernel_filename); 240 } 241 242 static void openrisc_sim_machine_init(ObjectClass *oc, void *data) 243 { 244 MachineClass *mc = MACHINE_CLASS(oc); 245 246 mc->desc = "or1k simulation"; 247 mc->init = openrisc_sim_init; 248 mc->max_cpus = OR1KSIM_CPUS_MAX; 249 mc->is_default = true; 250 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 251 } 252 253 static const TypeInfo or1ksim_machine_typeinfo = { 254 .name = TYPE_OR1KSIM_MACHINE, 255 .parent = TYPE_MACHINE, 256 .class_init = openrisc_sim_machine_init, 257 .instance_size = sizeof(Or1ksimState), 258 }; 259 260 static void or1ksim_machine_init_register_types(void) 261 { 262 type_register_static(&or1ksim_machine_typeinfo); 263 } 264 265 type_init(or1ksim_machine_init_register_types) 266