1 /* 2 * OpenRISC simulator for use as an IIS. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/irq.h" 26 #include "hw/boards.h" 27 #include "elf.h" 28 #include "hw/char/serial.h" 29 #include "net/net.h" 30 #include "hw/loader.h" 31 #include "hw/qdev-properties.h" 32 #include "exec/address-spaces.h" 33 #include "sysemu/device_tree.h" 34 #include "sysemu/sysemu.h" 35 #include "hw/sysbus.h" 36 #include "sysemu/qtest.h" 37 #include "sysemu/reset.h" 38 #include "hw/core/split-irq.h" 39 40 #include <libfdt.h> 41 42 #define KERNEL_LOAD_ADDR 0x100 43 44 #define OR1KSIM_CPUS_MAX 4 45 #define OR1KSIM_CLK_MHZ 20000000 46 47 #define TYPE_OR1KSIM_MACHINE MACHINE_TYPE_NAME("or1k-sim") 48 #define OR1KSIM_MACHINE(obj) \ 49 OBJECT_CHECK(Or1ksimState, (obj), TYPE_OR1KSIM_MACHINE) 50 51 typedef struct Or1ksimState { 52 /*< private >*/ 53 MachineState parent_obj; 54 55 /*< public >*/ 56 void *fdt; 57 int fdt_size; 58 59 } Or1ksimState; 60 61 enum { 62 OR1KSIM_DRAM, 63 OR1KSIM_UART, 64 OR1KSIM_ETHOC, 65 OR1KSIM_OMPIC, 66 }; 67 68 enum { 69 OR1KSIM_OMPIC_IRQ = 1, 70 OR1KSIM_UART_IRQ = 2, 71 OR1KSIM_ETHOC_IRQ = 4, 72 }; 73 74 enum { 75 OR1KSIM_UART_COUNT = 4 76 }; 77 78 static const struct MemmapEntry { 79 hwaddr base; 80 hwaddr size; 81 } or1ksim_memmap[] = { 82 [OR1KSIM_DRAM] = { 0x00000000, 0 }, 83 [OR1KSIM_UART] = { 0x90000000, 0x100 }, 84 [OR1KSIM_ETHOC] = { 0x92000000, 0x800 }, 85 [OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 }, 86 }; 87 88 static struct openrisc_boot_info { 89 uint32_t bootstrap_pc; 90 uint32_t fdt_addr; 91 } boot_info; 92 93 static void main_cpu_reset(void *opaque) 94 { 95 OpenRISCCPU *cpu = opaque; 96 CPUState *cs = CPU(cpu); 97 98 cpu_reset(CPU(cpu)); 99 100 cpu_set_pc(cs, boot_info.bootstrap_pc); 101 cpu_set_gpr(&cpu->env, 3, boot_info.fdt_addr); 102 } 103 104 static qemu_irq get_cpu_irq(OpenRISCCPU *cpus[], int cpunum, int irq_pin) 105 { 106 return qdev_get_gpio_in_named(DEVICE(cpus[cpunum]), "IRQ", irq_pin); 107 } 108 109 static void openrisc_create_fdt(Or1ksimState *state, 110 const struct MemmapEntry *memmap, 111 int num_cpus, uint64_t mem_size, 112 const char *cmdline) 113 { 114 void *fdt; 115 int cpu; 116 char *nodename; 117 int pic_ph; 118 119 fdt = state->fdt = create_device_tree(&state->fdt_size); 120 if (!fdt) { 121 error_report("create_device_tree() failed"); 122 exit(1); 123 } 124 125 qemu_fdt_setprop_string(fdt, "/", "compatible", "opencores,or1ksim"); 126 qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x1); 127 qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x1); 128 129 nodename = g_strdup_printf("/memory@%" HWADDR_PRIx, 130 memmap[OR1KSIM_DRAM].base); 131 qemu_fdt_add_subnode(fdt, nodename); 132 qemu_fdt_setprop_cells(fdt, nodename, "reg", 133 memmap[OR1KSIM_DRAM].base, mem_size); 134 qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory"); 135 g_free(nodename); 136 137 qemu_fdt_add_subnode(fdt, "/cpus"); 138 qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); 139 qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); 140 141 for (cpu = 0; cpu < num_cpus; cpu++) { 142 nodename = g_strdup_printf("/cpus/cpu@%d", cpu); 143 qemu_fdt_add_subnode(fdt, nodename); 144 qemu_fdt_setprop_string(fdt, nodename, "compatible", 145 "opencores,or1200-rtlsvn481"); 146 qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); 147 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 148 OR1KSIM_CLK_MHZ); 149 g_free(nodename); 150 } 151 152 nodename = (char *)"/pic"; 153 qemu_fdt_add_subnode(fdt, nodename); 154 pic_ph = qemu_fdt_alloc_phandle(fdt); 155 qemu_fdt_setprop_string(fdt, nodename, "compatible", 156 "opencores,or1k-pic-level"); 157 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); 158 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 159 qemu_fdt_setprop_cell(fdt, nodename, "phandle", pic_ph); 160 161 qemu_fdt_setprop_cell(fdt, "/", "interrupt-parent", pic_ph); 162 163 qemu_fdt_add_subnode(fdt, "/chosen"); 164 if (cmdline) { 165 qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); 166 } 167 168 /* Create aliases node for use by devices. */ 169 qemu_fdt_add_subnode(fdt, "/aliases"); 170 } 171 172 static void openrisc_sim_net_init(Or1ksimState *state, hwaddr base, hwaddr size, 173 int num_cpus, OpenRISCCPU *cpus[], 174 int irq_pin, NICInfo *nd) 175 { 176 void *fdt = state->fdt; 177 DeviceState *dev; 178 SysBusDevice *s; 179 char *nodename; 180 int i; 181 182 dev = qdev_new("open_eth"); 183 qdev_set_nic_properties(dev, nd); 184 185 s = SYS_BUS_DEVICE(dev); 186 sysbus_realize_and_unref(s, &error_fatal); 187 if (num_cpus > 1) { 188 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 189 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 190 qdev_realize_and_unref(splitter, NULL, &error_fatal); 191 for (i = 0; i < num_cpus; i++) { 192 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 193 } 194 sysbus_connect_irq(s, 0, qdev_get_gpio_in(splitter, 0)); 195 } else { 196 sysbus_connect_irq(s, 0, get_cpu_irq(cpus, 0, irq_pin)); 197 } 198 sysbus_mmio_map(s, 0, base); 199 sysbus_mmio_map(s, 1, base + 0x400); 200 201 /* Init device tree node for ethoc. */ 202 nodename = g_strdup_printf("/ethoc@%" HWADDR_PRIx, base); 203 qemu_fdt_add_subnode(fdt, nodename); 204 qemu_fdt_setprop_string(fdt, nodename, "compatible", "opencores,ethoc"); 205 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 206 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 207 qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); 208 209 qemu_fdt_setprop_string(fdt, "/aliases", "enet0", nodename); 210 g_free(nodename); 211 } 212 213 static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base, 214 hwaddr size, int num_cpus, 215 OpenRISCCPU *cpus[], int irq_pin) 216 { 217 void *fdt = state->fdt; 218 DeviceState *dev; 219 SysBusDevice *s; 220 char *nodename; 221 int i; 222 223 dev = qdev_new("or1k-ompic"); 224 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 225 226 s = SYS_BUS_DEVICE(dev); 227 sysbus_realize_and_unref(s, &error_fatal); 228 for (i = 0; i < num_cpus; i++) { 229 sysbus_connect_irq(s, i, get_cpu_irq(cpus, i, irq_pin)); 230 } 231 sysbus_mmio_map(s, 0, base); 232 233 /* Add device tree node for ompic. */ 234 nodename = g_strdup_printf("/ompic@%" HWADDR_PRIx, base); 235 qemu_fdt_add_subnode(fdt, nodename); 236 qemu_fdt_setprop_string(fdt, nodename, "compatible", "openrisc,ompic"); 237 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 238 qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); 239 qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 0); 240 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 241 g_free(nodename); 242 } 243 244 static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base, 245 hwaddr size, int num_cpus, 246 OpenRISCCPU *cpus[], int irq_pin, 247 int uart_idx) 248 { 249 void *fdt = state->fdt; 250 char *nodename; 251 qemu_irq serial_irq; 252 char alias[sizeof("uart0")]; 253 int i; 254 255 if (num_cpus > 1) { 256 DeviceState *splitter = qdev_new(TYPE_SPLIT_IRQ); 257 qdev_prop_set_uint32(splitter, "num-lines", num_cpus); 258 qdev_realize_and_unref(splitter, NULL, &error_fatal); 259 for (i = 0; i < num_cpus; i++) { 260 qdev_connect_gpio_out(splitter, i, get_cpu_irq(cpus, i, irq_pin)); 261 } 262 serial_irq = qdev_get_gpio_in(splitter, 0); 263 } else { 264 serial_irq = get_cpu_irq(cpus, 0, irq_pin); 265 } 266 serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200, 267 serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1), 268 DEVICE_NATIVE_ENDIAN); 269 270 /* Add device tree node for serial. */ 271 nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base); 272 qemu_fdt_add_subnode(fdt, nodename); 273 qemu_fdt_setprop_string(fdt, nodename, "compatible", "ns16550a"); 274 qemu_fdt_setprop_cells(fdt, nodename, "reg", base, size); 275 qemu_fdt_setprop_cell(fdt, nodename, "interrupts", irq_pin); 276 qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", OR1KSIM_CLK_MHZ); 277 qemu_fdt_setprop(fdt, nodename, "big-endian", NULL, 0); 278 279 /* The /chosen node is created during fdt creation. */ 280 qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); 281 snprintf(alias, sizeof(alias), "uart%d", uart_idx); 282 qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename); 283 g_free(nodename); 284 } 285 286 static hwaddr openrisc_load_kernel(ram_addr_t ram_size, 287 const char *kernel_filename) 288 { 289 long kernel_size; 290 uint64_t elf_entry; 291 uint64_t high_addr; 292 hwaddr entry; 293 294 if (kernel_filename && !qtest_enabled()) { 295 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 296 &elf_entry, NULL, &high_addr, NULL, 1, 297 EM_OPENRISC, 1, 0); 298 entry = elf_entry; 299 if (kernel_size < 0) { 300 kernel_size = load_uimage(kernel_filename, 301 &entry, NULL, NULL, NULL, NULL); 302 high_addr = entry + kernel_size; 303 } 304 if (kernel_size < 0) { 305 kernel_size = load_image_targphys(kernel_filename, 306 KERNEL_LOAD_ADDR, 307 ram_size - KERNEL_LOAD_ADDR); 308 high_addr = KERNEL_LOAD_ADDR + kernel_size; 309 } 310 311 if (entry <= 0) { 312 entry = KERNEL_LOAD_ADDR; 313 } 314 315 if (kernel_size < 0) { 316 error_report("couldn't load the kernel '%s'", kernel_filename); 317 exit(1); 318 } 319 boot_info.bootstrap_pc = entry; 320 321 return high_addr; 322 } 323 return 0; 324 } 325 326 static hwaddr openrisc_load_initrd(Or1ksimState *state, const char *filename, 327 hwaddr load_start, uint64_t mem_size) 328 { 329 void *fdt = state->fdt; 330 int size; 331 hwaddr start; 332 333 /* We put the initrd right after the kernel; page aligned. */ 334 start = TARGET_PAGE_ALIGN(load_start); 335 336 size = load_ramdisk(filename, start, mem_size - start); 337 if (size < 0) { 338 size = load_image_targphys(filename, start, mem_size - start); 339 if (size < 0) { 340 error_report("could not load ramdisk '%s'", filename); 341 exit(1); 342 } 343 } 344 345 qemu_fdt_setprop_cell(fdt, "/chosen", 346 "linux,initrd-start", start); 347 qemu_fdt_setprop_cell(fdt, "/chosen", 348 "linux,initrd-end", start + size); 349 350 return start + size; 351 } 352 353 static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start, 354 uint64_t mem_size) 355 { 356 void *fdt = state->fdt; 357 uint32_t fdt_addr; 358 int ret; 359 int fdtsize = fdt_totalsize(fdt); 360 361 if (fdtsize <= 0) { 362 error_report("invalid device-tree"); 363 exit(1); 364 } 365 366 /* We put fdt right after the kernel and/or initrd. */ 367 fdt_addr = TARGET_PAGE_ALIGN(load_start); 368 369 ret = fdt_pack(fdt); 370 /* Should only fail if we've built a corrupted tree */ 371 g_assert(ret == 0); 372 /* copy in the device tree */ 373 qemu_fdt_dumpdtb(fdt, fdtsize); 374 375 rom_add_blob_fixed_as("fdt", fdt, fdtsize, fdt_addr, 376 &address_space_memory); 377 378 return fdt_addr; 379 } 380 381 static void openrisc_sim_init(MachineState *machine) 382 { 383 ram_addr_t ram_size = machine->ram_size; 384 const char *kernel_filename = machine->kernel_filename; 385 OpenRISCCPU *cpus[OR1KSIM_CPUS_MAX] = {}; 386 Or1ksimState *state = OR1KSIM_MACHINE(machine); 387 MemoryRegion *ram; 388 hwaddr load_addr; 389 int n; 390 unsigned int smp_cpus = machine->smp.cpus; 391 392 assert(smp_cpus >= 1 && smp_cpus <= OR1KSIM_CPUS_MAX); 393 for (n = 0; n < smp_cpus; n++) { 394 cpus[n] = OPENRISC_CPU(cpu_create(machine->cpu_type)); 395 if (cpus[n] == NULL) { 396 fprintf(stderr, "Unable to find CPU definition!\n"); 397 exit(1); 398 } 399 400 cpu_openrisc_clock_init(cpus[n]); 401 402 qemu_register_reset(main_cpu_reset, cpus[n]); 403 } 404 405 ram = g_malloc(sizeof(*ram)); 406 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 407 memory_region_add_subregion(get_system_memory(), 0, ram); 408 409 openrisc_create_fdt(state, or1ksim_memmap, smp_cpus, machine->ram_size, 410 machine->kernel_cmdline); 411 412 if (nd_table[0].used) { 413 openrisc_sim_net_init(state, or1ksim_memmap[OR1KSIM_ETHOC].base, 414 or1ksim_memmap[OR1KSIM_ETHOC].size, 415 smp_cpus, cpus, 416 OR1KSIM_ETHOC_IRQ, nd_table); 417 } 418 419 if (smp_cpus > 1) { 420 openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base, 421 or1ksim_memmap[OR1KSIM_OMPIC].size, 422 smp_cpus, cpus, OR1KSIM_OMPIC_IRQ); 423 } 424 425 for (n = 0; n < OR1KSIM_UART_COUNT; ++n) 426 openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base + 427 or1ksim_memmap[OR1KSIM_UART].size * n, 428 or1ksim_memmap[OR1KSIM_UART].size, 429 smp_cpus, cpus, OR1KSIM_UART_IRQ, n); 430 431 load_addr = openrisc_load_kernel(ram_size, kernel_filename); 432 if (load_addr > 0) { 433 if (machine->initrd_filename) { 434 load_addr = openrisc_load_initrd(state, machine->initrd_filename, 435 load_addr, machine->ram_size); 436 } 437 boot_info.fdt_addr = openrisc_load_fdt(state, load_addr, 438 machine->ram_size); 439 } 440 } 441 442 static void openrisc_sim_machine_init(ObjectClass *oc, void *data) 443 { 444 MachineClass *mc = MACHINE_CLASS(oc); 445 446 mc->desc = "or1k simulation"; 447 mc->init = openrisc_sim_init; 448 mc->max_cpus = OR1KSIM_CPUS_MAX; 449 mc->is_default = true; 450 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 451 } 452 453 static const TypeInfo or1ksim_machine_typeinfo = { 454 .name = TYPE_OR1KSIM_MACHINE, 455 .parent = TYPE_MACHINE, 456 .class_init = openrisc_sim_machine_init, 457 .instance_size = sizeof(Or1ksimState), 458 }; 459 460 static void or1ksim_machine_init_register_types(void) 461 { 462 type_register_static(&or1ksim_machine_typeinfo); 463 } 464 465 type_init(or1ksim_machine_init_register_types) 466