1 /* 2 * OpenRISC simulator for use as an IIS. 3 * 4 * Copyright (c) 2011-2012 Jia Liu <proljc@gmail.com> 5 * Feng Gao <gf91597@gmail.com> 6 * 7 * This library is free software; you can redistribute it and/or 8 * modify it under the terms of the GNU Lesser General Public 9 * License as published by the Free Software Foundation; either 10 * version 2.1 of the License, or (at your option) any later version. 11 * 12 * This library is distributed in the hope that it will be useful, 13 * but WITHOUT ANY WARRANTY; without even the implied warranty of 14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU 15 * Lesser General Public License for more details. 16 * 17 * You should have received a copy of the GNU Lesser General Public 18 * License along with this library; if not, see <http://www.gnu.org/licenses/>. 19 */ 20 21 #include "qemu/osdep.h" 22 #include "qemu/error-report.h" 23 #include "qapi/error.h" 24 #include "cpu.h" 25 #include "hw/hw.h" 26 #include "hw/boards.h" 27 #include "elf.h" 28 #include "hw/char/serial.h" 29 #include "net/net.h" 30 #include "hw/loader.h" 31 #include "exec/address-spaces.h" 32 #include "sysemu/sysemu.h" 33 #include "hw/sysbus.h" 34 #include "sysemu/qtest.h" 35 36 #define KERNEL_LOAD_ADDR 0x100 37 38 static struct openrisc_boot_info { 39 uint32_t bootstrap_pc; 40 } boot_info; 41 42 static void main_cpu_reset(void *opaque) 43 { 44 OpenRISCCPU *cpu = opaque; 45 CPUState *cs = CPU(cpu); 46 47 cpu_reset(CPU(cpu)); 48 49 cpu_set_pc(cs, boot_info.bootstrap_pc); 50 } 51 52 static void openrisc_sim_net_init(hwaddr base, hwaddr descriptors, 53 int num_cpus, qemu_irq **cpu_irqs, 54 int irq_pin, NICInfo *nd) 55 { 56 DeviceState *dev; 57 SysBusDevice *s; 58 int i; 59 60 dev = qdev_create(NULL, "open_eth"); 61 qdev_set_nic_properties(dev, nd); 62 qdev_init_nofail(dev); 63 64 s = SYS_BUS_DEVICE(dev); 65 for (i = 0; i < num_cpus; i++) { 66 sysbus_connect_irq(s, 0, cpu_irqs[i][irq_pin]); 67 } 68 sysbus_mmio_map(s, 0, base); 69 sysbus_mmio_map(s, 1, descriptors); 70 } 71 72 static void openrisc_sim_ompic_init(hwaddr base, int num_cpus, 73 qemu_irq **cpu_irqs, int irq_pin) 74 { 75 DeviceState *dev; 76 SysBusDevice *s; 77 int i; 78 79 dev = qdev_create(NULL, "or1k-ompic"); 80 qdev_prop_set_uint32(dev, "num-cpus", num_cpus); 81 qdev_init_nofail(dev); 82 83 s = SYS_BUS_DEVICE(dev); 84 for (i = 0; i < num_cpus; i++) { 85 sysbus_connect_irq(s, i, cpu_irqs[i][irq_pin]); 86 } 87 sysbus_mmio_map(s, 0, base); 88 } 89 90 static void openrisc_load_kernel(ram_addr_t ram_size, 91 const char *kernel_filename) 92 { 93 long kernel_size; 94 uint64_t elf_entry; 95 hwaddr entry; 96 97 if (kernel_filename && !qtest_enabled()) { 98 kernel_size = load_elf(kernel_filename, NULL, NULL, NULL, 99 &elf_entry, NULL, NULL, 1, EM_OPENRISC, 100 1, 0); 101 entry = elf_entry; 102 if (kernel_size < 0) { 103 kernel_size = load_uimage(kernel_filename, 104 &entry, NULL, NULL, NULL, NULL); 105 } 106 if (kernel_size < 0) { 107 kernel_size = load_image_targphys(kernel_filename, 108 KERNEL_LOAD_ADDR, 109 ram_size - KERNEL_LOAD_ADDR); 110 } 111 112 if (entry <= 0) { 113 entry = KERNEL_LOAD_ADDR; 114 } 115 116 if (kernel_size < 0) { 117 error_report("couldn't load the kernel '%s'", kernel_filename); 118 exit(1); 119 } 120 boot_info.bootstrap_pc = entry; 121 } 122 } 123 124 static void openrisc_sim_init(MachineState *machine) 125 { 126 ram_addr_t ram_size = machine->ram_size; 127 const char *kernel_filename = machine->kernel_filename; 128 OpenRISCCPU *cpu = NULL; 129 MemoryRegion *ram; 130 qemu_irq *cpu_irqs[2]; 131 qemu_irq serial_irq; 132 int n; 133 134 for (n = 0; n < smp_cpus; n++) { 135 cpu = OPENRISC_CPU(cpu_create(machine->cpu_type)); 136 if (cpu == NULL) { 137 fprintf(stderr, "Unable to find CPU definition!\n"); 138 exit(1); 139 } 140 cpu_openrisc_pic_init(cpu); 141 cpu_irqs[n] = (qemu_irq *) cpu->env.irq; 142 143 cpu_openrisc_clock_init(cpu); 144 145 qemu_register_reset(main_cpu_reset, cpu); 146 } 147 148 ram = g_malloc(sizeof(*ram)); 149 memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); 150 memory_region_add_subregion(get_system_memory(), 0, ram); 151 152 if (nd_table[0].used) { 153 openrisc_sim_net_init(0x92000000, 0x92000400, smp_cpus, 154 cpu_irqs, 4, nd_table); 155 } 156 157 if (smp_cpus > 1) { 158 openrisc_sim_ompic_init(0x98000000, smp_cpus, cpu_irqs, 1); 159 160 serial_irq = qemu_irq_split(cpu_irqs[0][2], cpu_irqs[1][2]); 161 } else { 162 serial_irq = cpu_irqs[0][2]; 163 } 164 165 serial_mm_init(get_system_memory(), 0x90000000, 0, serial_irq, 166 115200, serial_hd(0), DEVICE_NATIVE_ENDIAN); 167 168 openrisc_load_kernel(ram_size, kernel_filename); 169 } 170 171 static void openrisc_sim_machine_init(MachineClass *mc) 172 { 173 mc->desc = "or1k simulation"; 174 mc->init = openrisc_sim_init; 175 mc->max_cpus = 2; 176 mc->is_default = 1; 177 mc->default_cpu_type = OPENRISC_CPU_TYPE_NAME("or1200"); 178 } 179 180 DEFINE_MACHINE("or1k-sim", openrisc_sim_machine_init) 181